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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id z24-20020a17090abd9800b002a56b3931dfsm11737859pjr.49.2024.04.24.16.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 16:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: "Edgar E . Iglesias" , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 28/33] target/cris: Use cris_fetch in translate_v10.c.inc Date: Wed, 24 Apr 2024 16:31:26 -0700 Message-Id: <20240424233131.988727-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424233131.988727-1-richard.henderson@linaro.org> References: <20240424233131.988727-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/translate.c | 1 - target/cris/translate_v10.c.inc | 30 +++++++++--------------------- 2 files changed, 9 insertions(+), 22 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index bb2d6612ba..a30c67eb07 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -29,7 +29,6 @@ #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "mmu.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" #include "crisv32-decode.h" #include "qemu/qemu-print.h" diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc index 73fc27c15d..c15ff47505 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -165,20 +165,7 @@ static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc, /* Load [$rs] onto T1. */ if (is_imm) { - if (memsize != 4) { - if (s_ext) { - if (memsize == 1) - imm = cpu_ldsb_code(env, dc->pc + 2); - else - imm = cpu_ldsw_code(env, dc->pc + 2); - } else { - if (memsize == 1) - imm = cpu_ldub_code(env, dc->pc + 2); - else - imm = cpu_lduw_code(env, dc->pc + 2); - } - } else - imm = cpu_ldl_code(env, dc->pc + 2); + imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); tcg_gen_movi_tl(dst, imm); @@ -929,10 +916,11 @@ static int dec10_dip(CPUCRISState *env, DisasContext *dc) LOG_DIS("dip pc=%x opcode=%d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); if (dc->src == 15) { - imm = cpu_ldl_code(env, dc->pc + 2); + imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm); - if (dc->postinc) + if (dc->postinc) { insn_len += 4; + } tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); } else { gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0); @@ -1095,10 +1083,10 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) if (dc->src == 15) { LOG_DIS("jump.%d %d r%d r%d direct\n", size, dc->opcode, dc->src, dc->dst); - imm = cpu_ldl_code(env, dc->pc + 2); - if (dc->mode == CRISV10_MODE_AUTOINC) + imm = cris_fetch(env, dc, dc->pc + 2, size, 0); + if (dc->mode == CRISV10_MODE_AUTOINC) { insn_len += size; - + } c = tcg_constant_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); dc->jmp_pc = imm; @@ -1164,7 +1152,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) case CRISV10_IND_BCC_M: cris_cc_mask(dc, 0); - simm = cpu_ldsw_code(env, dc->pc + 2); + simm = cris_fetch(env, dc, dc->pc + 2, 2, 1); simm += 4; LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm); @@ -1185,7 +1173,7 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc) unsigned int insn_len = 2; /* Load a halfword onto the instruction register. */ - dc->ir = cpu_lduw_code(env, dc->pc); + dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); /* Now decode it. */ dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);