@@ -103,8 +103,8 @@ typedef enum ResetType {
* the callback.
*/
typedef void (*ResettableEnterPhase)(Object *obj, ResetType type);
-typedef void (*ResettableHoldPhase)(Object *obj);
-typedef void (*ResettableExitPhase)(Object *obj);
+typedef void (*ResettableHoldPhase)(Object *obj, ResetType type);
+typedef void (*ResettableExitPhase)(Object *obj, ResetType type);
typedef ResettableState * (*ResettableGetState)(Object *obj);
typedef void (*ResettableTrFunction)(Object *obj);
typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj);
@@ -218,7 +218,7 @@ static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
npcm7xx_adc_reset(s);
}
-static void npcm7xx_adc_hold_reset(Object *obj)
+static void npcm7xx_adc_hold_reset(Object *obj, ResetType type)
{
NPCM7xxADCState *s = NPCM7XX_ADC(obj);
@@ -272,7 +272,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
-static void pxa2xx_pic_reset_hold(Object *obj)
+static void pxa2xx_pic_reset_hold(Object *obj, ResetType type)
{
PXA2xxPICState *s = PXA2XX_PIC(obj);
@@ -682,7 +682,7 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
}
}
-static void smmu_base_reset_hold(Object *obj)
+static void smmu_base_reset_hold(Object *obj, ResetType type)
{
SMMUState *s = ARM_SMMU(obj);
@@ -1727,13 +1727,13 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
}
}
-static void smmu_reset_hold(Object *obj)
+static void smmu_reset_hold(Object *obj, ResetType type)
{
SMMUv3State *s = ARM_SMMUV3(obj);
SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
if (c->parent_phases.hold) {
- c->parent_phases.hold(obj);
+ c->parent_phases.hold(obj, type);
}
smmuv3_init_regs(s);
@@ -394,7 +394,7 @@ static void stellaris_sys_reset_enter(Object *obj, ResetType type)
s->dcgc[0] = 1;
}
-static void stellaris_sys_reset_hold(Object *obj)
+static void stellaris_sys_reset_hold(Object *obj, ResetType type)
{
ssys_state *s = STELLARIS_SYS(obj);
@@ -402,7 +402,7 @@ static void stellaris_sys_reset_hold(Object *obj)
ssys_calculate_system_clock(s, true);
}
-static void stellaris_sys_reset_exit(Object *obj)
+static void stellaris_sys_reset_exit(Object *obj, ResetType type)
{
}
@@ -618,7 +618,7 @@ static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
i2c_end_transfer(s->bus);
}
-static void stellaris_i2c_reset_hold(Object *obj)
+static void stellaris_i2c_reset_hold(Object *obj, ResetType type)
{
stellaris_i2c_state *s = STELLARIS_I2C(obj);
@@ -631,7 +631,7 @@ static void stellaris_i2c_reset_hold(Object *obj)
s->mcr = 0;
}
-static void stellaris_i2c_reset_exit(Object *obj)
+static void stellaris_i2c_reset_exit(Object *obj, ResetType type)
{
stellaris_i2c_state *s = STELLARIS_I2C(obj);
@@ -787,7 +787,7 @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
}
}
-static void stellaris_adc_reset_hold(Object *obj)
+static void stellaris_adc_reset_hold(Object *obj, ResetType type)
{
StellarisADCState *s = STELLARIS_ADC(obj);
int n;
@@ -610,7 +610,7 @@ static void asc_fifo_init(ASCFIFOState *fs, int index)
g_free(name);
}
-static void asc_reset_hold(Object *obj)
+static void asc_reset_hold(Object *obj, ResetType type)
{
ASCState *s = ASC(obj);
@@ -525,7 +525,7 @@ static void cadence_uart_reset_init(Object *obj, ResetType type)
s->r[R_TTRIG] = 0x00000020;
}
-static void cadence_uart_reset_hold(Object *obj)
+static void cadence_uart_reset_hold(Object *obj, ResetType type)
{
CadenceUARTState *s = CADENCE_UART(obj);
@@ -214,7 +214,7 @@ static void sifive_uart_reset_enter(Object *obj, ResetType type)
s->rx_fifo_len = 0;
}
-static void sifive_uart_reset_hold(Object *obj)
+static void sifive_uart_reset_hold(Object *obj, ResetType type)
{
SiFiveUARTState *s = SIFIVE_UART(obj);
qemu_irq_lower(s->irq);
@@ -113,7 +113,7 @@ void cpu_reset(CPUState *cpu)
trace_cpu_reset(cpu->cpu_index);
}
-static void cpu_common_reset_hold(Object *obj)
+static void cpu_common_reset_hold(Object *obj, ResetType type)
{
CPUState *cpu = CPU(obj);
CPUClass *cc = CPU_GET_CLASS(cpu);
@@ -760,10 +760,10 @@ static void device_phases_reset(DeviceState *dev)
rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
}
if (rc->phases.hold) {
- rc->phases.hold(OBJECT(dev));
+ rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD);
}
if (rc->phases.exit) {
- rc->phases.exit(OBJECT(dev));
+ rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD);
}
}
@@ -73,7 +73,7 @@ static ResettableState *legacy_reset_get_state(Object *obj)
return &lr->reset_state;
}
-static void legacy_reset_hold(Object *obj)
+static void legacy_reset_hold(Object *obj, ResetType type)
{
LegacyReset *lr = LEGACY_RESET(obj);
@@ -181,7 +181,7 @@ static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
trace_resettable_transitional_function(obj, obj_typename);
tr_func(obj);
} else if (rc->phases.hold) {
- rc->phases.hold(obj);
+ rc->phases.hold(obj, type);
}
}
trace_resettable_phase_hold_end(obj, obj_typename, s->count);
@@ -204,7 +204,7 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
if (--s->count == 0) {
trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
- rc->phases.exit(obj);
+ rc->phases.exit(obj, type);
}
}
s->exit_phase_in_progress = false;
@@ -180,14 +180,14 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
}
}
-static void virtio_vga_base_reset_hold(Object *obj)
+static void virtio_vga_base_reset_hold(Object *obj, ResetType type)
{
VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
/* reset virtio-gpu */
if (klass->parent_phases.hold) {
- klass->parent_phases.hold(obj);
+ klass->parent_phases.hold(obj, type);
}
/* reset vga */
@@ -352,7 +352,7 @@ static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
}
-static void npcm7xx_gpio_hold_reset(Object *obj)
+static void npcm7xx_gpio_hold_reset(Object *obj, ResetType type)
{
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
@@ -484,7 +484,7 @@ static void pl061_enter_reset(Object *obj, ResetType type)
s->amsel = 0;
}
-static void pl061_hold_reset(Object *obj)
+static void pl061_hold_reset(Object *obj, ResetType type)
{
PL061State *s = PL061(obj);
int i, level;
@@ -70,7 +70,7 @@ static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
return extract32(s->otyper, pin, 1) == 0;
}
-static void stm32l4x5_gpio_reset_hold(Object *obj)
+static void stm32l4x5_gpio_reset_hold(Object *obj, ResetType type)
{
Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
@@ -2453,7 +2453,7 @@ static void vmbus_unrealize(BusState *bus)
qemu_mutex_destroy(&vmbus->rx_queue_lock);
}
-static void vmbus_reset_hold(Object *obj)
+static void vmbus_reset_hold(Object *obj, ResetType type)
{
vmbus_deinit(VMBUS(obj));
}
@@ -170,7 +170,7 @@ static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
return s->cntr & TWI_CNTR_INT_EN;
}
-static void allwinner_i2c_reset_hold(Object *obj)
+static void allwinner_i2c_reset_hold(Object *obj, ResetType type)
{
AWI2CState *s = AW_I2C(obj);
@@ -1022,7 +1022,7 @@ static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type)
s->rx_cur = 0;
}
-static void npcm7xx_smbus_hold_reset(Object *obj)
+static void npcm7xx_smbus_hold_reset(Object *obj, ResetType type)
{
NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj);
@@ -231,7 +231,7 @@ static const VMStateDescription vmstate_adb_bus = {
}
};
-static void adb_bus_reset_hold(Object *obj)
+static void adb_bus_reset_hold(Object *obj, ResetType type)
{
ADBBusState *adb_bus = ADB_BUS(obj);
@@ -1007,7 +1007,7 @@ void ps2_write_mouse(PS2MouseState *s, int val)
}
}
-static void ps2_reset_hold(Object *obj)
+static void ps2_reset_hold(Object *obj, ResetType type)
{
PS2State *s = PS2_DEVICE(obj);
@@ -1015,7 +1015,7 @@ static void ps2_reset_hold(Object *obj)
ps2_reset_queue(s);
}
-static void ps2_reset_exit(Object *obj)
+static void ps2_reset_exit(Object *obj, ResetType type)
{
PS2State *s = PS2_DEVICE(obj);
@@ -1048,7 +1048,7 @@ static void ps2_common_post_load(PS2State *s)
q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1;
}
-static void ps2_kbd_reset_hold(Object *obj)
+static void ps2_kbd_reset_hold(Object *obj, ResetType type)
{
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
PS2KbdState *s = PS2_KBD_DEVICE(obj);
@@ -1056,7 +1056,7 @@ static void ps2_kbd_reset_hold(Object *obj)
trace_ps2_kbd_reset(s);
if (ps2dc->parent_phases.hold) {
- ps2dc->parent_phases.hold(obj);
+ ps2dc->parent_phases.hold(obj, type);
}
s->scan_enabled = 1;
@@ -1065,7 +1065,7 @@ static void ps2_kbd_reset_hold(Object *obj)
s->modifiers = 0;
}
-static void ps2_mouse_reset_hold(Object *obj)
+static void ps2_mouse_reset_hold(Object *obj, ResetType type)
{
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
PS2MouseState *s = PS2_MOUSE_DEVICE(obj);
@@ -1073,7 +1073,7 @@ static void ps2_mouse_reset_hold(Object *obj)
trace_ps2_mouse_reset(s);
if (ps2dc->parent_phases.hold) {
- ps2dc->parent_phases.hold(obj);
+ ps2dc->parent_phases.hold(obj, type);
}
s->mouse_status = 0;
@@ -263,7 +263,7 @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int cidx,
}
}
-static void arm_gic_common_reset_hold(Object *obj)
+static void arm_gic_common_reset_hold(Object *obj, ResetType type)
{
GICState *s = ARM_GIC_COMMON(obj);
int i, j;
@@ -473,13 +473,13 @@ static void kvm_arm_gic_get(GICState *s)
}
}
-static void kvm_arm_gic_reset_hold(Object *obj)
+static void kvm_arm_gic_reset_hold(Object *obj, ResetType type)
{
GICState *s = ARM_GIC_COMMON(obj);
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
if (kgc->parent_phases.hold) {
- kgc->parent_phases.hold(obj);
+ kgc->parent_phases.hold(obj, type);
}
if (kvm_arm_gic_can_save_restore(s)) {
@@ -495,7 +495,7 @@ static void arm_gicv3_finalize(Object *obj)
g_free(s->redist_region_count);
}
-static void arm_gicv3_common_reset_hold(Object *obj)
+static void arm_gicv3_common_reset_hold(Object *obj, ResetType type)
{
GICv3State *s = ARM_GICV3_COMMON(obj);
int i;
@@ -1950,13 +1950,13 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
}
}
-static void gicv3_its_reset_hold(Object *obj)
+static void gicv3_its_reset_hold(Object *obj, ResetType type)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
if (c->parent_phases.hold) {
- c->parent_phases.hold(obj);
+ c->parent_phases.hold(obj, type);
}
/* Quiescent bit reset to 1 */
@@ -123,7 +123,7 @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
msi_nonbroken = true;
}
-static void gicv3_its_common_reset_hold(Object *obj)
+static void gicv3_its_common_reset_hold(Object *obj, ResetType type)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
@@ -197,14 +197,14 @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
GITS_CTLR, &s->ctlr, true, &error_abort);
}
-static void kvm_arm_its_reset_hold(Object *obj)
+static void kvm_arm_its_reset_hold(Object *obj, ResetType type)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
int i;
if (c->parent_phases.hold) {
- c->parent_phases.hold(obj);
+ c->parent_phases.hold(obj, type);
}
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
@@ -703,7 +703,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
}
-static void kvm_arm_gicv3_reset_hold(Object *obj)
+static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type)
{
GICv3State *s = ARM_GICV3_COMMON(obj);
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
@@ -711,7 +711,7 @@ static void kvm_arm_gicv3_reset_hold(Object *obj)
DPRINTF("Reset\n");
if (kgc->parent_phases.hold) {
- kgc->parent_phases.hold(obj);
+ kgc->parent_phases.hold(obj, type);
}
if (s->migration_blocker) {
@@ -579,7 +579,7 @@ static void ics_reset_irq(ICSIRQState *irq)
irq->saved_priority = 0xff;
}
-static void ics_reset_hold(Object *obj)
+static void ics_reset_hold(Object *obj, ResetType type)
{
ICSState *ics = ICS(obj);
g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
@@ -175,7 +175,7 @@ static void glue_nmi_release(void *opaque)
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
}
-static void glue_reset_hold(Object *obj)
+static void glue_reset_hold(Object *obj, ResetType type)
{
GLUEState *s = GLUE(obj);
@@ -96,7 +96,7 @@ static void djmemc_init(Object *obj)
sysbus_init_mmio(sbd, &s->mem_regs);
}
-static void djmemc_reset_hold(Object *obj)
+static void djmemc_reset_hold(Object *obj, ResetType type)
{
DJMEMCState *s = DJMEMC(obj);
@@ -81,7 +81,7 @@ static const MemoryRegionOps iosb_mmio_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void iosb_reset_hold(Object *obj)
+static void iosb_reset_hold(Object *obj, ResetType type)
{
IOSBState *s = IOSB(obj);
@@ -1203,7 +1203,7 @@ static int via1_post_load(void *opaque, int version_id)
}
/* VIA 1 */
-static void mos6522_q800_via1_reset_hold(Object *obj)
+static void mos6522_q800_via1_reset_hold(Object *obj, ResetType type)
{
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
MOS6522State *ms = MOS6522(v1s);
@@ -1211,7 +1211,7 @@ static void mos6522_q800_via1_reset_hold(Object *obj)
ADBBusState *adb_bus = &v1s->adb_bus;
if (mdc->parent_phases.hold) {
- mdc->parent_phases.hold(obj);
+ mdc->parent_phases.hold(obj, type);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
@@ -1359,13 +1359,13 @@ static void mos6522_q800_via2_portB_write(MOS6522State *s)
}
}
-static void mos6522_q800_via2_reset_hold(Object *obj)
+static void mos6522_q800_via2_reset_hold(Object *obj, ResetType type)
{
MOS6522State *ms = MOS6522(obj);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
if (mdc->parent_phases.hold) {
- mdc->parent_phases.hold(obj);
+ mdc->parent_phases.hold(obj, type);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
@@ -586,13 +586,13 @@ static void mos6522_cuda_portB_write(MOS6522State *s)
cuda_update(cs);
}
-static void mos6522_cuda_reset_hold(Object *obj)
+static void mos6522_cuda_reset_hold(Object *obj, ResetType type)
{
MOS6522State *ms = MOS6522(obj);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
if (mdc->parent_phases.hold) {
- mdc->parent_phases.hold(obj);
+ mdc->parent_phases.hold(obj, type);
}
ms->timers[0].frequency = CUDA_TIMER_FREQ;
@@ -792,7 +792,7 @@ static void mos6522_pmu_portB_write(MOS6522State *s)
pmu_update(ps);
}
-static void mos6522_pmu_reset_hold(Object *obj)
+static void mos6522_pmu_reset_hold(Object *obj, ResetType type)
{
MOS6522State *ms = MOS6522(obj);
MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
@@ -800,7 +800,7 @@ static void mos6522_pmu_reset_hold(Object *obj)
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
if (mdc->parent_phases.hold) {
- mdc->parent_phases.hold(obj);
+ mdc->parent_phases.hold(obj, type);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
@@ -642,7 +642,7 @@ const VMStateDescription vmstate_mos6522 = {
}
};
-static void mos6522_reset_hold(Object *obj)
+static void mos6522_reset_hold(Object *obj, ResetType type)
{
MOS6522State *s = MOS6522(obj);
@@ -467,7 +467,7 @@ static void npcm7xx_mft_enter_reset(Object *obj, ResetType type)
npcm7xx_mft_reset(s);
}
-static void npcm7xx_mft_hold_reset(Object *obj)
+static void npcm7xx_mft_hold_reset(Object *obj, ResetType type)
{
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
@@ -468,7 +468,7 @@ static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
s->piir = 0x00000000;
}
-static void npcm7xx_pwm_hold_reset(Object *obj)
+static void npcm7xx_pwm_hold_reset(Object *obj, ResetType type)
{
NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
int i;
@@ -77,7 +77,7 @@ static unsigned configurable_mask(unsigned bank)
return valid_mask(bank) & ~exti_romask[bank];
}
-static void stm32l4x5_exti_reset_hold(Object *obj)
+static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type)
{
Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj);
@@ -113,13 +113,13 @@ static void clock_mux_reset_enter(Object *obj, ResetType type)
set_clock_mux_init_info(s, s->id);
}
-static void clock_mux_reset_hold(Object *obj)
+static void clock_mux_reset_hold(Object *obj, ResetType type)
{
RccClockMuxState *s = RCC_CLOCK_MUX(obj);
clock_mux_update(s, true);
}
-static void clock_mux_reset_exit(Object *obj)
+static void clock_mux_reset_exit(Object *obj, ResetType type)
{
RccClockMuxState *s = RCC_CLOCK_MUX(obj);
clock_mux_update(s, false);
@@ -263,13 +263,13 @@ static void pll_reset_enter(Object *obj, ResetType type)
set_pll_init_info(s, s->id);
}
-static void pll_reset_hold(Object *obj)
+static void pll_reset_hold(Object *obj, ResetType type)
{
RccPllState *s = RCC_PLL(obj);
pll_update(s, true);
}
-static void pll_reset_exit(Object *obj)
+static void pll_reset_exit(Object *obj, ResetType type)
{
RccPllState *s = RCC_PLL(obj);
pll_update(s, false);
@@ -907,7 +907,7 @@ static void rcc_update_csr(Stm32l4x5RccState *s)
rcc_update_irq(s);
}
-static void stm32l4x5_rcc_reset_hold(Object *obj)
+static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type)
{
Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
s->cr = 0x00000063;
@@ -65,7 +65,7 @@
#define NUM_LINES_PER_EXTICR_REG 4
-static void stm32l4x5_syscfg_hold_reset(Object *obj)
+static void stm32l4x5_syscfg_hold_reset(Object *obj, ResetType type)
{
Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
@@ -542,7 +542,7 @@ static void cframe_reg_reset_enter(Object *obj, ResetType type)
}
}
-static void cframe_reg_reset_hold(Object *obj)
+static void cframe_reg_reset_hold(Object *obj, ResetType type)
{
XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj);
@@ -311,7 +311,7 @@ static void crl_reset_enter(Object *obj, ResetType type)
}
}
-static void crl_reset_hold(Object *obj)
+static void crl_reset_hold(Object *obj, ResetType type)
{
XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
@@ -1350,7 +1350,7 @@ static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type)
}
}
-static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj)
+static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj, ResetType type)
{
XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);
@@ -632,7 +632,7 @@ static void trng_unrealize(DeviceState *dev)
s->prng = NULL;
}
-static void trng_reset_hold(Object *obj)
+static void trng_reset_hold(Object *obj, ResetType type)
{
trng_reset(XLNX_VERSAL_TRNG(obj));
}
@@ -137,7 +137,7 @@ static void xram_ctrl_reset_enter(Object *obj, ResetType type)
ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size);
}
-static void xram_ctrl_reset_hold(Object *obj)
+static void xram_ctrl_reset_hold(Object *obj, ResetType type)
{
XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
@@ -150,7 +150,7 @@ static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
s->cpu_in_wfi = 0;
}
-static void zynqmp_apu_reset_hold(Object *obj)
+static void zynqmp_apu_reset_hold(Object *obj, ResetType type)
{
XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
@@ -191,7 +191,7 @@ static void crf_reset_enter(Object *obj, ResetType type)
}
}
-static void crf_reset_hold(Object *obj)
+static void crf_reset_hold(Object *obj, ResetType type)
{
XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
ir_update_irq(s);
@@ -416,7 +416,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type)
s->regs[R_DDRIOB + 12] = 0x00000021;
}
-static void zynq_slcr_reset_hold(Object *obj)
+static void zynq_slcr_reset_hold(Object *obj, ResetType type)
{
ZynqSLCRState *s = ZYNQ_SLCR(obj);
@@ -425,7 +425,7 @@ static void zynq_slcr_reset_hold(Object *obj)
zynq_slcr_propagate_clocks(s);
}
-static void zynq_slcr_reset_exit(Object *obj)
+static void zynq_slcr_reset_exit(Object *obj, ResetType type)
{
ZynqSLCRState *s = ZYNQ_SLCR(obj);
@@ -1006,7 +1006,7 @@ static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
ptimer_transaction_commit(s->can_timer);
}
-static void xlnx_zynqmp_can_reset_hold(Object *obj)
+static void xlnx_zynqmp_can_reset_hold(Object *obj, ResetType type)
{
XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
unsigned int i;
@@ -373,7 +373,7 @@ static bool e1000_vet_init_need(void *opaque)
return chkflag(VET);
}
-static void e1000_reset_hold(Object *obj)
+static void e1000_reset_hold(Object *obj, ResetType type)
{
E1000State *d = E1000(obj);
E1000BaseClass *edc = E1000_GET_CLASS(d);
@@ -513,7 +513,7 @@ static void e1000e_pci_uninit(PCIDevice *pci_dev)
msi_uninit(pci_dev);
}
-static void e1000e_qdev_reset_hold(Object *obj)
+static void e1000e_qdev_reset_hold(Object *obj, ResetType type)
{
E1000EState *s = E1000E(obj);
@@ -486,7 +486,7 @@ static void igb_pci_uninit(PCIDevice *pci_dev)
msi_uninit(pci_dev);
}
-static void igb_qdev_reset_hold(Object *obj)
+static void igb_qdev_reset_hold(Object *obj, ResetType type)
{
IGBState *s = IGB(obj);
@@ -282,7 +282,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
pcie_ari_init(dev, 0x150);
}
-static void igbvf_qdev_reset_hold(Object *obj)
+static void igbvf_qdev_reset_hold(Object *obj, ResetType type)
{
PCIDevice *vf = PCI_DEVICE(obj);
@@ -417,7 +417,7 @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
}
};
-static void bbram_ctrl_reset_hold(Object *obj)
+static void bbram_ctrl_reset_hold(Object *obj, ResetType type)
{
XlnxBBRam *s = XLNX_BBRAM(obj);
unsigned int i;
@@ -658,7 +658,7 @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
register_reset(reg);
}
-static void efuse_ctrl_reset_hold(Object *obj)
+static void efuse_ctrl_reset_hold(Object *obj, ResetType type)
{
XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
unsigned int i;
@@ -770,7 +770,7 @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
register_reset(reg);
}
-static void zynqmp_efuse_reset_hold(Object *obj)
+static void zynqmp_efuse_reset_hold(Object *obj, ResetType type)
{
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
unsigned int i;
@@ -186,13 +186,13 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
component_bar);
}
-static void cxl_rp_reset_hold(Object *obj)
+static void cxl_rp_reset_hold(Object *obj, ResetType type)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
CXLRootPort *crp = CXL_ROOT_PORT(obj);
if (rpc->parent_phases.hold) {
- rpc->parent_phases.hold(obj);
+ rpc->parent_phases.hold(obj, type);
}
latch_registers(crp);
@@ -43,7 +43,7 @@ static void rp_write_config(PCIDevice *d, uint32_t address,
pcie_aer_root_write_config(d, address, val, len, root_cmd);
}
-static void rp_reset_hold(Object *obj)
+static void rp_reset_hold(Object *obj, ResetType type)
{
PCIDevice *d = PCI_DEVICE(obj);
DeviceState *qdev = DEVICE(obj);
@@ -590,7 +590,7 @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
}
}
-static void bonito_reset_hold(Object *obj)
+static void bonito_reset_hold(Object *obj, ResetType type)
{
PCIBonitoState *s = PCI_BONITO(obj);
uint32_t val = 0;
@@ -208,7 +208,7 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
dc->user_creatable = true;
}
-static void pnv_phb_root_port_reset_hold(Object *obj)
+static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
@@ -216,7 +216,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj)
uint8_t *conf = d->config;
if (rpc->parent_phases.hold) {
- rpc->parent_phases.hold(obj);
+ rpc->parent_phases.hold(obj, type);
}
if (phb_rp->version == 3) {
@@ -228,13 +228,13 @@ static void phb3_msi_resend(ICSState *ics)
}
}
-static void phb3_msi_reset_hold(Object *obj)
+static void phb3_msi_reset_hold(Object *obj, ResetType type)
{
Phb3MsiState *msi = PHB3_MSI(obj);
ICSStateClass *icsc = ICS_GET_CLASS(obj);
if (icsc->parent_phases.hold) {
- icsc->parent_phases.hold(obj);
+ icsc->parent_phases.hold(obj, type);
}
memset(msi->rba, 0, sizeof(msi->rba));
@@ -64,7 +64,7 @@ bool pci_available = true;
static char *pcibus_get_dev_path(DeviceState *dev);
static char *pcibus_get_fw_dev_path(DeviceState *dev);
-static void pcibus_reset_hold(Object *obj);
+static void pcibus_reset_hold(Object *obj, ResetType type);
static bool pcie_has_upstream_port(PCIDevice *dev);
static Property pci_props[] = {
@@ -427,7 +427,7 @@ void pci_device_reset(PCIDevice *dev)
* Called via bus_cold_reset on RST# assert, after the devices
* have been reset device_cold_reset-ed already.
*/
-static void pcibus_reset_hold(Object *obj)
+static void pcibus_reset_hold(Object *obj, ResetType type)
{
PCIBus *bus = PCI_BUS(obj);
int i;
@@ -998,7 +998,7 @@ static void rtc_reset_enter(Object *obj, ResetType type)
}
}
-static void rtc_reset_hold(Object *obj)
+static void rtc_reset_hold(Object *obj, ResetType type)
{
MC146818RtcState *s = MC146818_RTC(obj);
@@ -56,7 +56,7 @@ static void ccw_device_unplug(HotplugHandler *hotplug_dev,
qdev_unrealize(dev);
}
-static void virtual_css_bus_reset_hold(Object *obj)
+static void virtual_css_bus_reset_hold(Object *obj, ResetType type)
{
/* This should actually be modelled via the generic css */
css_reset();
@@ -76,7 +76,7 @@ static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66};
static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0,
0x0, 0x07, 0x41, 0x30};
-static void adm1266_exit_reset(Object *obj)
+static void adm1266_exit_reset(Object *obj, ResetType type)
{
ADM1266State *s = ADM1266(obj);
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
@@ -185,7 +185,7 @@ static uint32_t adm1272_direct_to_watts(uint16_t value)
return pmbus_direct_mode2data(c, value);
}
-static void adm1272_exit_reset(Object *obj)
+static void adm1272_exit_reset(Object *obj, ResetType type)
{
ADM1272State *s = ADM1272(obj);
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
@@ -63,7 +63,7 @@ static void isl_pmbus_vr_set(Object *obj, Visitor *v, const char *name,
pmbus_check_limits(pmdev);
}
-static void isl_pmbus_vr_exit_reset(Object *obj)
+static void isl_pmbus_vr_exit_reset(Object *obj, ResetType type)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
@@ -102,11 +102,11 @@ static void isl_pmbus_vr_exit_reset(Object *obj)
}
/* The raa228000 uses different direct mode coefficients from most isl devices */
-static void raa228000_exit_reset(Object *obj)
+static void raa228000_exit_reset(Object *obj, ResetType type)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
- isl_pmbus_vr_exit_reset(obj);
+ isl_pmbus_vr_exit_reset(obj, type);
pmdev->pages[0].read_iout = 0;
pmdev->pages[0].read_pout = 0;
@@ -119,13 +119,13 @@ static void raa228000_exit_reset(Object *obj)
pmdev->pages[0].read_temperature_3 = 0;
}
-static void isl69259_exit_reset(Object *obj)
+static void isl69259_exit_reset(Object *obj, ResetType type)
{
ISLState *s = ISL69260(obj);
static const uint8_t ic_device_id[] = {0x04, 0x00, 0x81, 0xD2, 0x49, 0x3c};
g_assert(sizeof(ic_device_id) <= sizeof(s->ic_device_id));
- isl_pmbus_vr_exit_reset(obj);
+ isl_pmbus_vr_exit_reset(obj, type);
s->ic_device_id_len = sizeof(ic_device_id);
memcpy(s->ic_device_id, ic_device_id, sizeof(ic_device_id));
@@ -444,7 +444,7 @@ static int max31785_write_data(PMBusDevice *pmdev, const uint8_t *buf,
return 0;
}
-static void max31785_exit_reset(Object *obj)
+static void max31785_exit_reset(Object *obj, ResetType type)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
MAX31785State *s = MAX31785(obj);
@@ -608,7 +608,7 @@ static inline void *memset_word(void *s, uint16_t c, size_t n)
return s;
}
-static void max34451_exit_reset(Object *obj)
+static void max34451_exit_reset(Object *obj, ResetType type)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
MAX34451State *s = MAX34451(obj);
@@ -483,7 +483,7 @@ static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
}
-static void npcm7xx_fiu_hold_reset(Object *obj)
+static void npcm7xx_fiu_hold_reset(Object *obj, ResetType type)
{
NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
int i;
@@ -357,7 +357,7 @@ static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
t->rw_intr_mask = 0;
}
-static void etraxfs_timer_reset_hold(Object *obj)
+static void etraxfs_timer_reset_hold(Object *obj, ResetType type)
{
ETRAXTimerState *t = ETRAX_TIMER(obj);
@@ -592,7 +592,7 @@ static void npcm7xx_watchdog_timer_expired(void *opaque)
}
}
-static void npcm7xx_timer_hold_reset(Object *obj)
+static void npcm7xx_timer_hold_reset(Object *obj, ResetType type)
{
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
int i;
@@ -1305,7 +1305,7 @@ static void dwc2_reset_enter(Object *obj, ResetType type)
}
}
-static void dwc2_reset_hold(Object *obj)
+static void dwc2_reset_hold(Object *obj, ResetType type)
{
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
DWC2State *s = DWC2_USB(obj);
@@ -1313,13 +1313,13 @@ static void dwc2_reset_hold(Object *obj)
trace_usb_dwc2_reset_hold();
if (c->parent_phases.hold) {
- c->parent_phases.hold(obj);
+ c->parent_phases.hold(obj, type);
}
dwc2_update_irq(s);
}
-static void dwc2_reset_exit(Object *obj)
+static void dwc2_reset_exit(Object *obj, ResetType type)
{
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
DWC2State *s = DWC2_USB(obj);
@@ -1327,7 +1327,7 @@ static void dwc2_reset_exit(Object *obj)
trace_usb_dwc2_reset_exit();
if (c->parent_phases.exit) {
- c->parent_phases.exit(obj);
+ c->parent_phases.exit(obj, type);
}
s->hprt0 = HPRT0_PWR;
@@ -153,7 +153,7 @@ static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
}
}
-static void usb2_ctrl_regs_reset_hold(Object *obj)
+static void usb2_ctrl_regs_reset_hold(Object *obj, ResetType type)
{
VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
@@ -2292,7 +2292,7 @@ static void virtio_pci_reset(DeviceState *qdev)
}
}
-static void virtio_pci_bus_reset_hold(Object *obj)
+static void virtio_pci_bus_reset_hold(Object *obj, ResetType type)
{
PCIDevice *dev = PCI_DEVICE(obj);
DeviceState *qdev = DEVICE(obj);
@@ -220,7 +220,7 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
assert(oldvalue == newvalue);
}
-static void arm_cpu_reset_hold(Object *obj)
+static void arm_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
ARMCPU *cpu = ARM_CPU(cs);
@@ -228,7 +228,7 @@ static void arm_cpu_reset_hold(Object *obj)
CPUARMState *env = &cpu->env;
if (acc->parent_phases.hold) {
- acc->parent_phases.hold(obj);
+ acc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUARMState, end_reset_fields));
@@ -66,7 +66,7 @@ static void avr_restore_state_to_opc(CPUState *cs,
cpu_env(cs)->pc_w = data[0];
}
-static void avr_cpu_reset_hold(Object *obj)
+static void avr_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
AVRCPU *cpu = AVR_CPU(cs);
@@ -74,7 +74,7 @@ static void avr_cpu_reset_hold(Object *obj)
CPUAVRState *env = &cpu->env;
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
env->pc_w = 0;
@@ -61,7 +61,7 @@ static int cris_cpu_mmu_index(CPUState *cs, bool ifetch)
return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG);
}
-static void cris_cpu_reset_hold(Object *obj)
+static void cris_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
@@ -69,7 +69,7 @@ static void cris_cpu_reset_hold(Object *obj)
uint32_t vr;
if (ccc->parent_phases.hold) {
- ccc->parent_phases.hold(obj);
+ ccc->parent_phases.hold(obj, type);
}
vr = env->pregs[PR_VR];
@@ -273,14 +273,14 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
}
-static void hexagon_cpu_reset_hold(Object *obj)
+static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
CPUHexagonState *env = cpu_env(cs);
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
set_default_nan_mode(1, &env->fp_status);
@@ -6830,7 +6830,7 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
#endif
}
-static void x86_cpu_reset_hold(Object *obj)
+static void x86_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(cs);
@@ -6841,7 +6841,7 @@ static void x86_cpu_reset_hold(Object *obj)
int i;
if (xcc->parent_phases.hold) {
- xcc->parent_phases.hold(obj);
+ xcc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
@@ -495,14 +495,14 @@ static void loongarch_max_initfn(Object *obj)
loongarch_la464_initfn(obj);
}
-static void loongarch_cpu_reset_hold(Object *obj)
+static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj);
CPULoongArchState *env = cpu_env(cs);
if (lacc->parent_phases.hold) {
- lacc->parent_phases.hold(obj);
+ lacc->parent_phases.hold(obj, type);
}
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
@@ -71,7 +71,7 @@ static void m68k_unset_feature(CPUM68KState *env, int feature)
env->features &= ~BIT_ULL(feature);
}
-static void m68k_cpu_reset_hold(Object *obj)
+static void m68k_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
@@ -80,7 +80,7 @@ static void m68k_cpu_reset_hold(Object *obj)
int i;
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
@@ -181,7 +181,7 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
}
#endif
-static void mb_cpu_reset_hold(Object *obj)
+static void mb_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
@@ -189,7 +189,7 @@ static void mb_cpu_reset_hold(Object *obj)
CPUMBState *env = &cpu->env;
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUMBState, end_reset_fields));
@@ -185,7 +185,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
#include "cpu-defs.c.inc"
-static void mips_cpu_reset_hold(Object *obj)
+static void mips_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -193,7 +193,7 @@ static void mips_cpu_reset_hold(Object *obj)
CPUMIPSState *env = &cpu->env;
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
@@ -85,14 +85,14 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
info->print_insn = print_insn_or1k;
}
-static void openrisc_cpu_reset_hold(Object *obj)
+static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj);
if (occ->parent_phases.hold) {
- occ->parent_phases.hold(obj);
+ occ->parent_phases.hold(obj, type);
}
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
@@ -7136,7 +7136,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
return ppc_env_mmu_index(cpu_env(cs), ifetch);
}
-static void ppc_cpu_reset_hold(Object *obj)
+static void ppc_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -7146,7 +7146,7 @@ static void ppc_cpu_reset_hold(Object *obj)
int i;
if (pcc->parent_phases.hold) {
- pcc->parent_phases.hold(obj);
+ pcc->parent_phases.hold(obj, type);
}
msr = (target_ulong)0;
@@ -918,7 +918,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
return riscv_env_mmu_index(cpu_env(cs), ifetch);
}
-static void riscv_cpu_reset_hold(Object *obj)
+static void riscv_cpu_reset_hold(Object *obj, ResetType type)
{
#ifndef CONFIG_USER_ONLY
uint8_t iprio;
@@ -930,7 +930,7 @@ static void riscv_cpu_reset_hold(Object *obj)
CPURISCVState *env = &cpu->env;
if (mcc->parent_phases.hold) {
- mcc->parent_phases.hold(obj);
+ mcc->parent_phases.hold(obj, type);
}
#ifndef CONFIG_USER_ONLY
env->misa_mxl = mcc->misa_mxl_max;
@@ -69,7 +69,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc)
return 0;
}
-static void rx_cpu_reset_hold(Object *obj)
+static void rx_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
@@ -77,7 +77,7 @@ static void rx_cpu_reset_hold(Object *obj)
uint32_t *resetvec;
if (rcc->parent_phases.hold) {
- rcc->parent_phases.hold(obj);
+ rcc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPURXState, end_reset_fields));
@@ -103,14 +103,14 @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
}
}
-static void superh_cpu_reset_hold(Object *obj)
+static void superh_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
CPUSH4State *env = cpu_env(cs);
if (scc->parent_phases.hold) {
- scc->parent_phases.hold(obj);
+ scc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
@@ -29,14 +29,14 @@
//#define DEBUG_FEATURES
-static void sparc_cpu_reset_hold(Object *obj)
+static void sparc_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
CPUSPARCState *env = cpu_env(cs);
if (scc->parent_phases.hold) {
- scc->parent_phases.hold(obj);
+ scc->parent_phases.hold(obj, type);
}
memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
@@ -58,13 +58,13 @@ static void tricore_restore_state_to_opc(CPUState *cs,
cpu_env(cs)->PC = data[0];
}
-static void tricore_cpu_reset_hold(Object *obj)
+static void tricore_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
if (tcc->parent_phases.hold) {
- tcc->parent_phases.hold(obj);
+ tcc->parent_phases.hold(obj, type);
}
cpu_state_reset(cpu_env(cs));
@@ -93,7 +93,7 @@ bool xtensa_abi_call0(void)
}
#endif
-static void xtensa_cpu_reset_hold(Object *obj)
+static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
@@ -102,7 +102,7 @@ static void xtensa_cpu_reset_hold(Object *obj)
XTENSA_OPTION_DFP_COPROCESSOR);
if (xcc->parent_phases.hold) {
- xcc->parent_phases.hold(obj);
+ xcc->parent_phases.hold(obj, type);
}
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that. Commit created with for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done and no manual edits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org --- include/hw/resettable.h | 4 ++-- hw/adc/npcm7xx_adc.c | 2 +- hw/arm/pxa2xx_pic.c | 2 +- hw/arm/smmu-common.c | 2 +- hw/arm/smmuv3.c | 4 ++-- hw/arm/stellaris.c | 10 +++++----- hw/audio/asc.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/sifive_uart.c | 2 +- hw/core/cpu-common.c | 2 +- hw/core/qdev.c | 4 ++-- hw/core/reset.c | 2 +- hw/core/resettable.c | 4 ++-- hw/display/virtio-vga.c | 4 ++-- hw/gpio/npcm7xx_gpio.c | 2 +- hw/gpio/pl061.c | 2 +- hw/gpio/stm32l4x5_gpio.c | 2 +- hw/hyperv/vmbus.c | 2 +- hw/i2c/allwinner-i2c.c | 2 +- hw/i2c/npcm7xx_smbus.c | 2 +- hw/input/adb.c | 2 +- hw/input/ps2.c | 12 ++++++------ hw/intc/arm_gic_common.c | 2 +- hw/intc/arm_gic_kvm.c | 4 ++-- hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_its.c | 4 ++-- hw/intc/arm_gicv3_its_common.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 4 ++-- hw/intc/arm_gicv3_kvm.c | 4 ++-- hw/intc/xics.c | 2 +- hw/m68k/q800-glue.c | 2 +- hw/misc/djmemc.c | 2 +- hw/misc/iosb.c | 2 +- hw/misc/mac_via.c | 8 ++++---- hw/misc/macio/cuda.c | 4 ++-- hw/misc/macio/pmu.c | 4 ++-- hw/misc/mos6522.c | 2 +- hw/misc/npcm7xx_mft.c | 2 +- hw/misc/npcm7xx_pwm.c | 2 +- hw/misc/stm32l4x5_exti.c | 2 +- hw/misc/stm32l4x5_rcc.c | 10 +++++----- hw/misc/stm32l4x5_syscfg.c | 2 +- hw/misc/xlnx-versal-cframe-reg.c | 2 +- hw/misc/xlnx-versal-crl.c | 2 +- hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +- hw/misc/xlnx-versal-trng.c | 2 +- hw/misc/xlnx-versal-xramc.c | 2 +- hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +- hw/misc/xlnx-zynqmp-crf.c | 2 +- hw/misc/zynq_slcr.c | 4 ++-- hw/net/can/xlnx-zynqmp-can.c | 2 +- hw/net/e1000.c | 2 +- hw/net/e1000e.c | 2 +- hw/net/igb.c | 2 +- hw/net/igbvf.c | 2 +- hw/nvram/xlnx-bbram.c | 2 +- hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +- hw/nvram/xlnx-zynqmp-efuse.c | 2 +- hw/pci-bridge/cxl_root_port.c | 4 ++-- hw/pci-bridge/pcie_root_port.c | 2 +- hw/pci-host/bonito.c | 2 +- hw/pci-host/pnv_phb.c | 4 ++-- hw/pci-host/pnv_phb3_msi.c | 4 ++-- hw/pci/pci.c | 4 ++-- hw/rtc/mc146818rtc.c | 2 +- hw/s390x/css-bridge.c | 2 +- hw/sensor/adm1266.c | 2 +- hw/sensor/adm1272.c | 2 +- hw/sensor/isl_pmbus_vr.c | 10 +++++----- hw/sensor/max31785.c | 2 +- hw/sensor/max34451.c | 2 +- hw/ssi/npcm7xx_fiu.c | 2 +- hw/timer/etraxfs_timer.c | 2 +- hw/timer/npcm7xx_timer.c | 2 +- hw/usb/hcd-dwc2.c | 8 ++++---- hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +- hw/virtio/virtio-pci.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 4 ++-- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 4 ++-- target/i386/cpu.c | 4 ++-- target/loongarch/cpu.c | 4 ++-- target/m68k/cpu.c | 4 ++-- target/microblaze/cpu.c | 4 ++-- target/mips/cpu.c | 4 ++-- target/openrisc/cpu.c | 4 ++-- target/ppc/cpu_init.c | 4 ++-- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 4 ++-- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 4 ++-- target/tricore/cpu.c | 4 ++-- target/xtensa/cpu.c | 4 ++-- 94 files changed, 150 insertions(+), 150 deletions(-)