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Sun, 28 Apr 2024 20:25:14 -0700 (PDT) Date: Mon, 29 Apr 2024 03:24:02 +0000 In-Reply-To: <20240429032403.74910-1-smostafa@google.com> Mime-Version: 1.0 References: <20240429032403.74910-1-smostafa@google.com> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog Message-ID: <20240429032403.74910-19-smostafa@google.com> Subject: [RFC PATCH v3 18/18] hw/arm/virt: Set SMMU OAS based on CPU PARANGE From: Mostafa Saleh To: qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org, Mostafa Saleh Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=3GhMvZggKCjUjdfjkRWRXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--smostafa.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use the new SMMU property to make the SMMU OAS match the CPU PARANGE. That's according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. Signed-off-by: Mostafa Saleh --- hw/arm/virt.c | 14 ++++++++++++-- target/arm/cpu.h | 2 ++ target/arm/cpu64.c | 5 +++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3c93c0c0a6..f203b1f8e1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -252,6 +252,13 @@ static bool ns_el2_virt_timer_present(void) arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); } +/* We rely on CPU to define system OAS. */ +static int32_t get_system_oas(void) +{ + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); + return cpu_arm_get_oas(cpu); +} + static void create_fdt(VirtMachineState *vms) { MachineState *ms = MACHINE(vms); @@ -1384,7 +1391,7 @@ static void create_pcie_irq_map(const MachineState *ms, } static void create_smmu(const VirtMachineState *vms, - PCIBus *bus) + PCIBus *bus, int32_t oas) { char *node; const char compat[] = "arm,smmu-v3"; @@ -1404,6 +1411,9 @@ static void create_smmu(const VirtMachineState *vms, object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); + + qdev_prop_set_uint64(dev, "oas", oas); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i = 0; i < NUM_SMMU_IRQS; i++) { @@ -1578,7 +1588,7 @@ static void create_pcie(VirtMachineState *vms) switch (vms->iommu) { case VIRT_IOMMU_SMMUV3: - create_smmu(vms, vms->bus); + create_smmu(vms, vms->bus, get_system_oas()); qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); break; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 17efc5d565..68261ffbf9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3287,4 +3287,6 @@ static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) } #endif +int32_t cpu_arm_get_oas(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 985b1efe16..08da83c082 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -787,6 +787,11 @@ static const gchar *aarch64_gdb_arch_name(CPUState *cs) return "aarch64"; } +int32_t cpu_arm_get_oas(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc);