@@ -77,6 +77,11 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx)
return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx;
}
+static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx)
+{
+ return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx;
+}
+
#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
KVM_REG_RISCV_CORE_REG(name))
@@ -88,7 +93,7 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx)
#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx)
-#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
+#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx)
#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
do { \
@@ -579,7 +584,7 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
if (riscv_has_ext(env, RVD)) {
uint64_t reg;
for (i = 0; i < 32; i++) {
- ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®);
if (ret) {
return ret;
}
@@ -613,7 +618,7 @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
uint64_t reg;
for (i = 0; i < 32; i++) {
reg = env->fpr[i];
- ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®);
if (ret) {
return ret;
}