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[176.184.10.250]) by smtp.gmail.com with ESMTPSA id o5-20020aa7c7c5000000b00572c25023b1sm7792892eds.0.2024.05.08.10.47.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 08 May 2024 10:47:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 23/26] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check Date: Wed, 8 May 2024 19:45:07 +0200 Message-ID: <20240508174510.60470-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240508174510.60470-1-philmd@linaro.org> References: <20240508174510.60470-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang Since cpuid will be checked by ipi_getcpu anyway, there is no point to enforce MAX_CPU here. This also saved us from including loongarch board header. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240508-loongson3-ipi-v1-1-1a7b67704664@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongarch_ipi.c | 19 ++----------------- hw/intc/trace-events | 2 -- 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index a184112b09..44b3b9c138 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -6,6 +6,7 @@ */ #include "qemu/osdep.h" +#include "hw/boards.h" #include "hw/sysbus.h" #include "hw/intc/loongarch_ipi.h" #include "hw/irq.h" @@ -13,9 +14,8 @@ #include "qapi/error.h" #include "qemu/log.h" #include "exec/address-spaces.h" -#include "hw/loongarch/virt.h" #include "migration/vmstate.h" -#include "target/loongarch/internals.h" +#include "target/loongarch/cpu.h" #include "trace.h" static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr, @@ -122,11 +122,6 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) CPUState *cs; cpuid = extract32(val, 16, 10); - if (cpuid >= LOONGARCH_MAX_CPUS) { - trace_loongarch_ipi_unsupported_cpuid("IOCSR_MAIL_SEND", cpuid); - return MEMTX_DECODE_ERROR; - } - cs = ipi_getcpu(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; @@ -146,11 +141,6 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) CPUState *cs; cpuid = extract32(val, 16, 10); - if (cpuid >= LOONGARCH_MAX_CPUS) { - trace_loongarch_ipi_unsupported_cpuid("IOCSR_ANY_SEND", cpuid); - return MEMTX_DECODE_ERROR; - } - cs = ipi_getcpu(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; @@ -201,11 +191,6 @@ static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, break; case IOCSR_IPI_SEND: cpuid = extract32(val, 16, 10); - if (cpuid >= LOONGARCH_MAX_CPUS) { - trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid); - return MEMTX_DECODE_ERROR; - } - /* IPI status vector */ vector = extract8(val, 0, 5); cs = ipi_getcpu(cpuid); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 47340b5bc1..a979784f9b 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -294,8 +294,6 @@ sh_intc_set(int id, int enable) "setting interrupt group %d to %d" # loongarch_ipi.c loongarch_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 loongarch_ipi_write(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 -loongarch_ipi_unsupported_cpuid(const char *s, uint32_t cpuid) "%s unsupported cpuid 0x%" PRIx32 - # loongarch_pch_pic.c loongarch_pch_pic_irq_handler(int irq, int level) "irq %d level %d" loongarch_pch_pic_low_readw(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64