diff mbox series

[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Message ID 20240510065856.2436870-4-fea.wang@sifive.com (mailing list archive)
State New
Headers show
Series target/riscv: Support RISC-V privilege 1.13 spec | expand

Commit Message

Fea.Wang May 10, 2024, 6:58 a.m. UTC 
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
SMSTATEEN0 that controls access to the hedeleg.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu_bits.h |  1 +
 target/riscv/csr.c      | 10 ++++++++++
 2 files changed, 11 insertions(+)

Comments

liwei May 11, 2024, 2:46 p.m. UTC | #1 
On 2024/5/10 14:58, Fea.Wang wrote:
> Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> SMSTATEEN0 that controls access to the hedeleg.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu_bits.h |  1 +
>   target/riscv/csr.c      | 10 ++++++++++
>   2 files changed, 11 insertions(+)
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>

Weiwei Li
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 74318a925c..28bd3fb0b4 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -315,6 +315,7 @@
>   #define SMSTATEEN0_CS       (1ULL << 0)
>   #define SMSTATEEN0_FCSR     (1ULL << 1)
>   #define SMSTATEEN0_JVT      (1ULL << 2)
> +#define SMSTATEEN0_P1P13    (1ULL << 56)
>   #define SMSTATEEN0_HSCONTXT (1ULL << 57)
>   #define SMSTATEEN0_IMSIC    (1ULL << 58)
>   #define SMSTATEEN0_AIA      (1ULL << 59)
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6b460ee0e8..d844ce770e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2248,6 +2248,11 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>           wr_mask |= SMSTATEEN0_FCSR;
>       }
>   
> +    RISCVCPU *cpu = env_archcpu(env);
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> +        wr_mask |= SMSTATEEN0_P1P13;
> +    }
> +
>       return write_mstateen(env, csrno, wr_mask, new_val);
>   }
>   
> @@ -2283,6 +2288,11 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
>   {
>       uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>   
> +    RISCVCPU *cpu = env_archcpu(env);
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> +            wr_mask |= SMSTATEEN0_P1P13;
> +    }
> +
>       return write_mstateenh(env, csrno, wr_mask, new_val);
>   }
>
LIU Zhiwei May 13, 2024, 2:51 a.m. UTC | #2 
On 2024/5/10 14:58, Fea.Wang wrote:
> Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> SMSTATEEN0 that controls access to the hedeleg.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu_bits.h |  1 +
>   target/riscv/csr.c      | 10 ++++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 74318a925c..28bd3fb0b4 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -315,6 +315,7 @@
>   #define SMSTATEEN0_CS       (1ULL << 0)
>   #define SMSTATEEN0_FCSR     (1ULL << 1)
>   #define SMSTATEEN0_JVT      (1ULL << 2)
> +#define SMSTATEEN0_P1P13    (1ULL << 56)
>   #define SMSTATEEN0_HSCONTXT (1ULL << 57)
>   #define SMSTATEEN0_IMSIC    (1ULL << 58)
>   #define SMSTATEEN0_AIA      (1ULL << 59)
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6b460ee0e8..d844ce770e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2248,6 +2248,11 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>           wr_mask |= SMSTATEEN0_FCSR;
>       }
>   
> +    RISCVCPU *cpu = env_archcpu(env);
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
Why not use env directly?
> +        wr_mask |= SMSTATEEN0_P1P13;
> +    }
> +
>       return write_mstateen(env, csrno, wr_mask, new_val);
>   }
>   
> @@ -2283,6 +2288,11 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
>   {
>       uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>   
> +    RISCVCPU *cpu = env_archcpu(env);
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
Same here.
> +            wr_mask |= SMSTATEEN0_P1P13;

Indent.

Zhiwei

> +    }
> +
>       return write_mstateenh(env, csrno, wr_mask, new_val);
>   }
>
Fea.Wang May 15, 2024, 7:46 a.m. UTC | #3 
Thank you, I will correct it in the patch v2.

Sincerely,
Fea

LIU Zhiwei <zhiwei_liu@linux.alibaba.com> 於 2024年5月13日 週一 上午10:51寫道：

>
> On 2024/5/10 14:58, Fea.Wang wrote:
> > Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> > SMSTATEEN0 that controls access to the hedeleg.
> >
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >   target/riscv/cpu_bits.h |  1 +
> >   target/riscv/csr.c      | 10 ++++++++++
> >   2 files changed, 11 insertions(+)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 74318a925c..28bd3fb0b4 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -315,6 +315,7 @@
> >   #define SMSTATEEN0_CS       (1ULL << 0)
> >   #define SMSTATEEN0_FCSR     (1ULL << 1)
> >   #define SMSTATEEN0_JVT      (1ULL << 2)
> > +#define SMSTATEEN0_P1P13    (1ULL << 56)
> >   #define SMSTATEEN0_HSCONTXT (1ULL << 57)
> >   #define SMSTATEEN0_IMSIC    (1ULL << 58)
> >   #define SMSTATEEN0_AIA      (1ULL << 59)
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 6b460ee0e8..d844ce770e 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -2248,6 +2248,11 @@ static RISCVException
> write_mstateen0(CPURISCVState *env, int csrno,
> >           wr_mask |= SMSTATEEN0_FCSR;
> >       }
> >
> > +    RISCVCPU *cpu = env_archcpu(env);
> > +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> Why not use env directly?
> > +        wr_mask |= SMSTATEEN0_P1P13;
> > +    }
> > +
> >       return write_mstateen(env, csrno, wr_mask, new_val);
> >   }
> >
> > @@ -2283,6 +2288,11 @@ static RISCVException
> write_mstateen0h(CPURISCVState *env, int csrno,
> >   {
> >       uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >
> > +    RISCVCPU *cpu = env_archcpu(env);
> > +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> Same here.
> > +            wr_mask |= SMSTATEEN0_P1P13;
>
> Indent.
>
> Zhiwei
>
> > +    }
> > +
> >       return write_mstateenh(env, csrno, wr_mask, new_val);
> >   }
> >
>
diff mbox series

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 74318a925c..28bd3fb0b4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -315,6 +315,7 @@ 
 #define SMSTATEEN0_CS       (1ULL << 0)
 #define SMSTATEEN0_FCSR     (1ULL << 1)
 #define SMSTATEEN0_JVT      (1ULL << 2)
+#define SMSTATEEN0_P1P13    (1ULL << 56)
 #define SMSTATEEN0_HSCONTXT (1ULL << 57)
 #define SMSTATEEN0_IMSIC    (1ULL << 58)
 #define SMSTATEEN0_AIA      (1ULL << 59)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6b460ee0e8..d844ce770e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2248,6 +2248,11 @@  static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
         wr_mask |= SMSTATEEN0_FCSR;
     }
 
+    RISCVCPU *cpu = env_archcpu(env);
+    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+        wr_mask |= SMSTATEEN0_P1P13;
+    }
+
     return write_mstateen(env, csrno, wr_mask, new_val);
 }
 
@@ -2283,6 +2288,11 @@  static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
 {
     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
+    RISCVCPU *cpu = env_archcpu(env);
+    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+            wr_mask |= SMSTATEEN0_P1P13;
+    }
+
     return write_mstateenh(env, csrno, wr_mask, new_val);
 }