| Message ID | 20240520125157.311503-3-rkanwal@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Minor fixes and improvements for Virtual IRQs | expand |
On 5/20/24 09:51, Rajnesh Kanwal wrote: > Qemu maps IRQs 0:15 for core interrupts and 16 onward for > guest interrupts which are later translated to hgiep in > `riscv_cpu_set_irq()` function. > > With virtual IRQ support added, software now can fully > use the whole local interrupt range without any actual > hardware attached. > > This change moves the guest interrupt range after the > core local interrupt range to avoid clash. > > Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") > Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu_bits.h | 3 ++- > target/riscv/csr.c | 9 ++++++++- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 74318a925c..a470fda9be 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -695,7 +695,8 @@ typedef enum RISCVException { > #define IRQ_M_EXT 11 > #define IRQ_S_GEXT 12 > #define IRQ_PMU_OVF 13 > -#define IRQ_LOCAL_MAX 16 > +#define IRQ_LOCAL_MAX 64 > +/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ > #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) > > /* mip masks */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 152796ebc0..464e0e57a3 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1148,7 +1148,14 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > > #define VSTOPI_NUM_SRCS 5 > > -#define LOCAL_INTERRUPTS (~0x1FFF) > +/* > + * All core local interrupts except the fixed ones 0:12. This macro is for > + * virtual interrupts logic so please don't change this to avoid messing up > + * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and > + * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for > + * VS level`. > + */ > +#define LOCAL_INTERRUPTS (~0x1FFFULL) > > static const uint64_t delegable_ints = > S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..a470fda9be 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -695,7 +695,8 @@ typedef enum RISCVException { #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 -#define IRQ_LOCAL_MAX 16 +#define IRQ_LOCAL_MAX 64 +/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) /* mip masks */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 152796ebc0..464e0e57a3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1148,7 +1148,14 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, #define VSTOPI_NUM_SRCS 5 -#define LOCAL_INTERRUPTS (~0x1FFF) +/* + * All core local interrupts except the fixed ones 0:12. This macro is for + * virtual interrupts logic so please don't change this to avoid messing up + * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and + * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for + * VS level`. + */ +#define LOCAL_INTERRUPTS (~0x1FFFULL) static const uint64_t delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> --- target/riscv/cpu_bits.h | 3 ++- target/riscv/csr.c | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-)