From patchwork Thu May 23 17:44:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 13672110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53CEDC25B75 for ; Thu, 23 May 2024 17:49:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sACZF-0006O8-OR; Thu, 23 May 2024 13:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sACYo-00060v-Ho for qemu-devel@nongnu.org; Thu, 23 May 2024 13:49:08 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sACYk-0003fC-Cj for qemu-devel@nongnu.org; Thu, 23 May 2024 13:49:02 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1f3469382f2so6218515ad.0 for ; Thu, 23 May 2024 10:48:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716486527; x=1717091327; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sP+37HoAbnRWxYkSxU+Q255kuctQLJ4X/JRVMf9ilwE=; b=E/jjpNgcXvTZP6CMVXT3WBmN9IZGrqA3/bXKIvbNmCz0HwUQyn/4GA9B2iGENZIkuP KFtg9Vz7ojR4fkco162X0O+mdxhoB/rO4AbnA4A497ie7mVGYaPEf/RanxmmE7SwlIHw OaVKhPlfW/paY5uL0vNvaY+0M4szzk51YmRBE/oKn6l86XIE9eEESeVp9dAAKaJwvK4X +MeOdyj9FtD147lCaeZaJ4QEmPOywsqW+s5xipL9RIsaXkRWKunDfo68pd0P3G2ndDOR x/2mJgDtKPUQ8OxR4hxiaLHWgk5gxsjPX/EZSw49TSpzBNIYv26qvCyv690IJq+SXAHy wxcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716486527; x=1717091327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sP+37HoAbnRWxYkSxU+Q255kuctQLJ4X/JRVMf9ilwE=; b=vfJQRF7/CuDwflE+JTSuBlB9T9bIekUjAai2W5Cgx8T2gtS219GTUKEfxtCdIgYwSA 8HlJBDaWekvXZYNzgisQt69wGi3Q7cN7XyR9M/vgro9B52TUI7LLFm3yVOrMsRzOWyoy c9BMl/uZlL8LXXkhk7szj5vUVqPl4bHmOp069KPM8Sqpo8PBa7mvA3Jj2EAhk2d9jPw/ 0RpBTNmMS3NaoLz4TEOieteS9iXozFv1ZY93yN1+Jj2rFCftXuCp42T7uWIF+LS8j00+ BH4TOThxcntXR5ieXDckdDe2yj/ZSuCVWgFOGrx6OC70cWhs0F0ogZO+bA9SbDwVyhfp yWjA== X-Gm-Message-State: AOJu0Yxaq/b8VtKLhE6tMCCnL6K28m+BiA5kpthpsJ8VL1uPzyqYxgFR 8c9OJzvHBGv/ziBf6VsNH3ogeB91iVKrI0XOMcibDhNYCdryaIkkXobaxg== X-Google-Smtp-Source: AGHT+IEe0mgnI5pXbKqlTk1fSEV++VaFM84jJggzb34ACdBzCaJNjvCav9SzhD1YF00KP+e8DzZwqw== X-Received: by 2002:a17:902:f549:b0:1f0:98f2:7cc6 with SMTP id d9443c01a7336-1f4497df612mr317095ad.45.1716486527371; Thu, 23 May 2024 10:48:47 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8f03:9fee:4f9e:216e:ed5a:642d]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c137e7esm253436265ad.257.2024.05.23.10.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 10:48:47 -0700 (PDT) From: nifan.cxl@gmail.com To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org, gregory.price@memverge.com, ira.weiny@intel.com, dan.j.williams@intel.com, a.manzanares@samsung.com, dave@stgolabs.net, nmtadam.samsung@gmail.com, nifan.cxl@gmail.com, jim.harris@samsung.com, Jorgen.Hansen@wdc.com, wj28.lee@gmail.com, armbru@redhat.com, mst@redhat.com, Fan Ni , Jonathan Cameron Subject: [PATCH v8 06/14] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices Date: Thu, 23 May 2024 10:44:46 -0700 Message-ID: <20240523174651.1089554-7-nifan.cxl@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523174651.1089554-1-nifan.cxl@gmail.com> References: <20240523174651.1089554-1-nifan.cxl@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=nifan.cxl@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni With the change, when setting up memory for type3 memory device, we can create DC regions. A property 'num-dc-regions' is added to ct3_props to allow users to pass the number of DC regions to create. To make it easier, other region parameters like region base, length, and block size are hard coded. If needed, these parameters can be added easily. With the change, we can create DC regions with proper kernel side support like below: region=$(cat /sys/bus/cxl/devices/decoder0.0/create_dc_region) echo $region > /sys/bus/cxl/devices/decoder0.0/create_dc_region echo 256 > /sys/bus/cxl/devices/$region/interleave_granularity echo 1 > /sys/bus/cxl/devices/$region/interleave_ways echo "dc0" >/sys/bus/cxl/devices/decoder2.0/mode echo 0x40000000 >/sys/bus/cxl/devices/decoder2.0/dpa_size echo 0x40000000 > /sys/bus/cxl/devices/$region/size echo "decoder2.0" > /sys/bus/cxl/devices/$region/target0 echo 1 > /sys/bus/cxl/devices/$region/commit echo $region > /sys/bus/cxl/drivers/cxl_region/bind Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Signed-off-by: Fan Ni Reviewed-by: Li Zhijian --- hw/mem/cxl_type3.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 7194c8f902..06c6f9bb78 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -30,6 +30,7 @@ #include "hw/pci/msix.h" #define DWORD_BYTE 4 +#define CXL_CAPACITY_MULTIPLIER (256 * MiB) /* Default CDAT entries for a memory region */ enum { @@ -567,6 +568,50 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, } } +/* + * TODO: dc region configuration will be updated once host backend and address + * space support is added for DCD. + */ +static bool cxl_create_dc_regions(CXLType3Dev *ct3d, Error **errp) +{ + int i; + uint64_t region_base = 0; + uint64_t region_len = 2 * GiB; + uint64_t decode_len = 2 * GiB; + uint64_t blk_size = 2 * MiB; + CXLDCRegion *region; + MemoryRegion *mr; + + if (ct3d->hostvmem) { + mr = host_memory_backend_get_memory(ct3d->hostvmem); + region_base += memory_region_size(mr); + } + if (ct3d->hostpmem) { + mr = host_memory_backend_get_memory(ct3d->hostpmem); + region_base += memory_region_size(mr); + } + if (region_base % CXL_CAPACITY_MULTIPLIER != 0) { + error_setg(errp, "DC region base not aligned to 0x%lx", + CXL_CAPACITY_MULTIPLIER); + return false; + } + + for (i = 0, region = &ct3d->dc.regions[0]; + i < ct3d->dc.num_regions; + i++, region++, region_base += region_len) { + *region = (CXLDCRegion) { + .base = region_base, + .decode_len = decode_len, + .len = region_len, + .block_size = blk_size, + /* dsmad_handle set when creating CDAT table entries */ + .flags = 0, + }; + } + + return true; +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); @@ -635,6 +680,13 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) g_free(p_name); } + if (ct3d->dc.num_regions > 0) { + if (!cxl_create_dc_regions(ct3d, errp)) { + error_append_hint(errp, "setup DC regions failed"); + return false; + } + } + return true; } @@ -930,6 +982,7 @@ static Property ct3_props[] = { HostMemoryBackend *), DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), + DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), DEFINE_PROP_END_OF_LIST(), };