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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fbf2cfd1sm1591695b3a.3.2024.05.24.16.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 16:25:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 49/67] target/arm: Convert SQRSHL, UQRSHL to decodetree Date: Fri, 24 May 2024 16:21:03 -0700 Message-Id: <20240524232121.284515-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524232121.284515-1-richard.henderson@linaro.org> References: <20240524232121.284515-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/a64.decode | 4 +++ target/arm/tcg/translate-a64.c | 48 ++++++++++++++++------------------ 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 85caf37948..96ce35ad40 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -762,6 +762,8 @@ SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e +SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e +UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e ### Advanced SIMD scalar pairwise @@ -890,6 +892,8 @@ SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e +SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e +UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e ### Advanced SIMD scalar x indexed element diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index b0004e2c6f..b76682cabf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5162,6 +5162,22 @@ static const ENVScalar2 f_scalar_uqshl = { }; TRANS(UQSHL_s, do_env_scalar2, a, &f_scalar_uqshl) +static const ENVScalar2 f_scalar_sqrshl = { + { gen_helper_neon_qrshl_s8, + gen_helper_neon_qrshl_s16, + gen_helper_neon_qrshl_s32 }, + gen_helper_neon_qrshl_s64, +}; +TRANS(SQRSHL_s, do_env_scalar2, a, &f_scalar_sqrshl) + +static const ENVScalar2 f_scalar_uqrshl = { + { gen_helper_neon_qrshl_u8, + gen_helper_neon_qrshl_u16, + gen_helper_neon_qrshl_u32 }, + gen_helper_neon_qrshl_u64, +}; +TRANS(UQRSHL_s, do_env_scalar2, a, &f_scalar_uqrshl) + static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, gen_helper_gvec_3_ptr * const fns[3]) { @@ -5413,6 +5429,8 @@ TRANS(SRSHL_v, do_gvec_fn3, a, gen_gvec_srshl) TRANS(URSHL_v, do_gvec_fn3, a, gen_gvec_urshl) TRANS(SQSHL_v, do_gvec_fn3, a, gen_neon_sqshl) TRANS(UQSHL_v, do_gvec_fn3, a, gen_neon_uqshl) +TRANS(SQRSHL_v, do_gvec_fn3, a, gen_neon_sqrshl) +TRANS(UQRSHL_v, do_gvec_fn3, a, gen_neon_uqrshl) /* @@ -9426,13 +9444,6 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, } gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); break; - case 0xb: /* SQRSHL, UQRSHL */ - if (u) { - gen_helper_neon_qrshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); - } else { - gen_helper_neon_qrshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); - } - break; case 0x10: /* ADD, SUB */ if (u) { tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); @@ -9446,6 +9457,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, case 0x8: /* SSHL, USHL */ case 0x9: /* SQSHL, UQSHL */ case 0xa: /* SRSHL, URSHL */ + case 0xb: /* SQRSHL, UQRSHL */ g_assert_not_reached(); } } @@ -9467,8 +9479,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) TCGv_i64 tcg_rd; switch (opcode) { - case 0xb: /* SQRSHL, UQRSHL */ - break; case 0x6: /* CMGT, CMHI */ case 0x7: /* CMGE, CMHS */ case 0x11: /* CMTST, CMEQ */ @@ -9490,6 +9500,7 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) case 0x8: /* SSHL, USHL */ case 0x9: /* SQSHL, UQSHL */ case 0xa: /* SRSHL, URSHL */ + case 0xb: /* SQRSHL, UQRSHL */ unallocated_encoding(s); return; } @@ -9516,16 +9527,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) void (*genfn)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, MemOp) = NULL; switch (opcode) { - case 0xb: /* SQRSHL, UQRSHL */ - { - static NeonGenTwoOpEnvFn * const fns[3][2] = { - { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, - { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, - { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, - }; - genenvfn = fns[size][u]; - break; - } case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] = { @@ -9540,6 +9541,7 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) case 0x1: /* SQADD, UQADD */ case 0x5: /* SQSUB, UQSUB */ case 0x9: /* SQSHL, UQSHL */ + case 0xb: /* SQRSHL, UQRSHL */ g_assert_not_reached(); } @@ -10965,13 +10967,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { - case 0x0b: /* SQRSHL, UQRSHL */ - if (u) { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_neon_uqrshl, size); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_neon_sqrshl, size); - } - return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); @@ -11055,6 +11050,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0x08: /* SSHL, USHL */ case 0x09: /* SQSHL, UQSHL */ case 0x0a: /* SRSHL, URSHL */ + case 0x0b: /* SQRSHL, UQRSHL */ g_assert_not_reached(); }