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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fcfe648bsm3457182b3a.168.2024.05.26.05.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 05:26:24 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Caleb Schlossin , =?utf-8?q?C=C3=A9dric_Le_Goate?= =?utf-8?q?r?= , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Date: Sun, 26 May 2024 22:26:02 +1000 Message-ID: <20240526122612.473476-2-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com> References: <20240526122612.473476-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=npiggin@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This helps move core state from CPU to core structures. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Reviewed-by: Harsh Prateek Bora --- include/hw/ppc/pnv_core.h | 1 + hw/ppc/pnv_core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c6d62fd145..30c1e5b1a3 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -54,6 +54,7 @@ struct PnvCoreClass { #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX typedef struct PnvCPUState { + PnvCore *core; Object *intc; } PnvCPUState; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index f40ab721d6..7b0ea7812b 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -225,6 +225,7 @@ static const MemoryRegionOps pnv_core_power10_xscom_ops = { static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, int thread_index) { + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); CPUPPCState *env = &cpu->env; int core_hwid; ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; @@ -232,6 +233,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, Error *local_err = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); + pnv_cpu->core = pc; + if (!qdev_realize(DEVICE(cpu), NULL, errp)) { return; }