diff mbox series

[RISU,v2,13/13] sparc64: Add VIS4 instructions

Message ID 20240526193637.459064-14-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series ELF and Sparc64 support | expand

Commit Message

Richard Henderson May 26, 2024, 7:36 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 sparc64.risu | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

Comments

Peter Maydell May 30, 2024, 1:25 p.m. UTC | #1 
On Sun, 26 May 2024 at 20:38, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  sparc64.risu | 46 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/sparc64.risu b/sparc64.risu
index 271fee0..1022a62 100644
--- a/sparc64.risu
+++ b/sparc64.risu
@@ -250,3 +250,49 @@  MOVxTOd         VIS3 10 rd:5 110110 00000 1 0001 1000 rs2:5 \
 
 FPMADDX         IMA 10 rd:5 110111 rs1:5 rs3:5 0000 rs2:5
 FPMADDXHI       IMA 10 rd:5 110111 rs1:5 rs3:5 0100 rs2:5
+
+#
+# VIS4
+#
+
+SUBXC           VIS4 10 rd:5 110110 rs1:5 0 0100 00 cc 1 rs2:5 \
+    !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); }
+
+FPADD8          VIS4 10 rd:5 110110 rs1:5 1 0010 0100 rs2:5
+FPADDS8         VIS4 10 rd:5 110110 rs1:5 1 0010 0110 rs2:5
+FPADDUS8        VIS4 10 rd:5 110110 rs1:5 1 0010 0111 rs2:5
+FPADDUS16       VIS4 10 rd:5 110110 rs1:5 1 0010 0011 rs2:5
+FPSUB8          VIS4 10 rd:5 110110 rs1:5 1 0101 0100 rs2:5
+FPSUBS8         VIS4 10 rd:5 110110 rs1:5 1 0101 0110 rs2:5
+FPSUBUS8        VIS4 10 rd:5 110110 rs1:5 1 0101 0111 rs2:5
+FPSUBUS16       VIS4 10 rd:5 110110 rs1:5 1 0101 0011 rs2:5
+
+FPMIN8          VIS4 10 rd:5 110110 rs1:5 1 0001 1010 rs2:5
+FPMIN16         VIS4 10 rd:5 110110 rs1:5 1 0001 1011 rs2:5
+FPMIN32         VIS4 10 rd:5 110110 rs1:5 1 0001 1100 rs2:5
+FPMINU8         VIS4 10 rd:5 110110 rs1:5 1 0101 1010 rs2:5
+FPMINU16        VIS4 10 rd:5 110110 rs1:5 1 0101 1011 rs2:5
+FPMINU32        VIS4 10 rd:5 110110 rs1:5 1 0101 1100 rs2:5
+
+FPMAX8          VIS4 10 rd:5 110110 rs1:5 1 0001 1101 rs2:5
+FPMAX16         VIS4 10 rd:5 110110 rs1:5 1 0001 1110 rs2:5
+FPMAX32         VIS4 10 rd:5 110110 rs1:5 1 0001 1111 rs2:5
+FPMAXU8         VIS4 10 rd:5 110110 rs1:5 1 0101 1101 rs2:5
+FPMAXU16        VIS4 10 rd:5 110110 rs1:5 1 0101 1110 rs2:5
+FPMAXU32        VIS4 10 rd:5 110110 rs1:5 1 0101 1111 rs2:5
+
+FPCMPLE8        VIS4 10 rd:5 110110 rs1:5 0 0011 0100 rs2:5 \
+    !constraints { reg_ok($rd) }
+FPCMPGT8        VIS4 10 rd:5 110110 rs1:5 0 0011 1100 rs2:5 \
+    !constraints { reg_ok($rd) }
+FPCMPULE16      VIS4 10 rd:5 110110 rs1:5 1 0010 1110 rs2:5 \
+    !constraints { reg_ok($rd) }
+FPCMPUGT16      VIS4 10 rd:5 110110 rs1:5 1 0010 1011 rs2:5 \
+    !constraints { reg_ok($rd) }
+FPCMPULE32      VIS4 10 rd:5 110110 rs1:5 1 0010 1111 rs2:5 \
+    !constraints { reg_ok($rd) }
+FPCMPUGT32      VIS4 10 rd:5 110110 rs1:5 1 0010 1100 rs2:5 \
+    !constraints { reg_ok($rd) }
+
+FALIGNDATAi     VIS4 10 rd:5 110110 rs1:5 0 0100 1001 rs2:5 \
+    !constraints { reg_ok($rs1); }