diff mbox series

[v2,03/37] target/sparc: Fix do_dc

Message ID	20240526194254.459395-4-richard.henderson@linaro.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 03/37] target/sparc: Fix do_dc Date: Sun, 26 May 2024 12:42:20 -0700 Message-Id: <20240526194254.459395-4-richard.henderson@linaro.org> In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	target/sparc: Implement VIS4 \| expand [v2,00/37] target/sparc: Implement VIS4 [v2,01/37] target/sparc: Fix ARRAY8 [v2,02/37] target/sparc: Rewrite gen_edge [v2,03/37] target/sparc: Fix do_dc [v2,04/37] target/sparc: Fix helper_fmul8ulx16 [v2,05/37] target/sparc: Perform DFPREG/QFPREG in decodetree [v2,06/37] target/sparc: Remove gen_dest_fpr_D [v2,07/37] target/sparc: Remove cpu_fpr[] [v2,08/37] target/sparc: Use gvec for VIS1 parallel add/sub [v2,09/37] target/sparc: Implement FMAf extension [v2,10/37] target/sparc: Add feature bits for VIS 3 [v2,11/37] target/sparc: Implement ADDXC, ADDXCcc [v2,12/37] target/sparc: Implement CMASK instructions [v2,13/37] target/sparc: Implement FCHKSM16 [v2,14/37] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL [v2,15/37] target/sparc: Implement FLCMP [v2,16/37] target/sparc: Implement FMEAN16 [v2,17/37] target/sparc: Implement FPADD64, FPSUB64 [v2,18/37] target/sparc: Implement FPADDS, FPSUBS [v2,19/37] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [v2,20/37] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [v2,21/37] target/sparc: Implement LDXEFSR [v2,22/37] target/sparc: Implement LZCNT [v2,23/37] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [v2,24/37] target/sparc: Implement PDISTN [v2,25/37] target/sparc: Implement UMULXHI [v2,26/37] target/sparc: Implement XMULX [v2,27/37] target/sparc: Enable VIS3 feature bit [v2,28/37] target/sparc: Implement IMA extension [v2,29/37] target/sparc: Add feature bit for VIS4 [v2,30/37] target/sparc: Implement FALIGNDATAi [v2,31/37] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [v2,32/37] target/sparc: Implement VIS4 comparisons [v2,33/37] target/sparc: Implement FPMIN, FPMAX [v2,34/37] target/sparc: Implement SUBXC, SUBXCcc [v2,35/37] target/sparc: Implement MWAIT [v2,36/37] target/sparc: Implement monitor ASIs [v2,37/37] target/sparc: Enable VIS4 feature bit

Commit Message

Richard Henderson May 26, 2024, 7:42 p.m. UTC

Apply DFPREG to compute the register number.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Philippe Mathieu-Daudé June 4, 2024, 11:41 a.m. UTC | #1

On 26/5/24 21:42, Richard Henderson wrote:
> Apply DFPREG to compute the register number.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sparc/translate.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

diff mbox series

Patch

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 00c2a11353..1eb1a6decf 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4253,6 +4253,7 @@  static bool do_dc(DisasContext *dc, int rd, int64_t c)
         return true;
     }
 
+    rd = DFPREG(rd);
     tcg_gen_movi_i64(cpu_fpr[rd / 2], c);
     gen_update_fprs_dirty(dc, rd);
     return advance_pc(dc);