| Message ID | 20240527124315.35356-1-clg@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | aspeed/smc: Reintroduce "dram-base" property for AST2700 | expand |
On 27/5/24 14:43, Cédric Le Goater wrote: > The Aspeed SMC device model use to have a 'sdram_base' property. It > was removed by commit d177892d4a48 ("aspeed/smc: Remove unused > "sdram-base" property") because previous changes simplified the DMA > transaction model to use an offset in RAM and not the physical > address. > > The AST2700 SoC has larger address space (64-bit) and a new register > DMA DRAM Side Address High Part (0x7C) is introduced to deal with the > high bits of the DMA address. To be able to compute the offset of the > DMA transaction, as done on the other SoCs, we will need to know where > the DRAM is mapped in the address space. Re-introduce a "dram-base" > property to hold this value. > > Signed-off-by: Cédric Le Goater <clg@redhat.com> > --- > include/hw/ssi/aspeed_smc.h | 1 + > hw/ssi/aspeed_smc.c | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > The Aspeed SMC device model use to have a 'sdram_base' property. It was > removed by commit d177892d4a48 ("aspeed/smc: Remove unused > "sdram-base" property") because previous changes simplified the DMA > transaction model to use an offset in RAM and not the physical address. > > The AST2700 SoC has larger address space (64-bit) and a new register DMA > DRAM Side Address High Part (0x7C) is introduced to deal with the high bits of > the DMA address. To be able to compute the offset of the DMA transaction, as > done on the other SoCs, we will need to know where the DRAM is mapped in > the address space. Re-introduce a "dram-base" > property to hold this value. > > Signed-off-by: Cédric Le Goater <clg@redhat.com> > --- > include/hw/ssi/aspeed_smc.h | 1 + > hw/ssi/aspeed_smc.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index > 8e1dda556b91..8791cc0ecb11 100644 > --- a/include/hw/ssi/aspeed_smc.h > +++ b/include/hw/ssi/aspeed_smc.h > @@ -76,6 +76,7 @@ struct AspeedSMCState { > AddressSpace flash_as; > MemoryRegion *dram_mr; > AddressSpace dram_as; > + uint64_t dram_base; > > AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX]; > > diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index > 6e1a84c19713..7075bc9d61b0 100644 > --- a/hw/ssi/aspeed_smc.c > +++ b/hw/ssi/aspeed_smc.c > @@ -1220,6 +1220,7 @@ static const VMStateDescription > vmstate_aspeed_smc = { > > static Property aspeed_smc_properties[] = { > DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, > false), > + DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), > DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, > TYPE_MEMORY_REGION, MemoryRegion *), > DEFINE_PROP_END_OF_LIST(), > -- > 2.45.1 Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Thanks-Jamin
On 5/27/24 2:43 PM, Cédric Le Goater wrote: > The Aspeed SMC device model use to have a 'sdram_base' property. It > was removed by commit d177892d4a48 ("aspeed/smc: Remove unused > "sdram-base" property") because previous changes simplified the DMA > transaction model to use an offset in RAM and not the physical > address. > > The AST2700 SoC has larger address space (64-bit) and a new register > DMA DRAM Side Address High Part (0x7C) is introduced to deal with the > high bits of the DMA address. To be able to compute the offset of the > DMA transaction, as done on the other SoCs, we will need to know where > the DRAM is mapped in the address space. Re-introduce a "dram-base" > property to hold this value. > > Signed-off-by: Cédric Le Goater <clg@redhat.com> > --- > include/hw/ssi/aspeed_smc.h | 1 + > hw/ssi/aspeed_smc.c | 1 + > 2 files changed, 2 insertions(+) Applied to aspeed-next. Thanks, C.
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 8e1dda556b91..8791cc0ecb11 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -76,6 +76,7 @@ struct AspeedSMCState { AddressSpace flash_as; MemoryRegion *dram_mr; AddressSpace dram_as; + uint64_t dram_base; AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX]; diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 6e1a84c19713..7075bc9d61b0 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1220,6 +1220,7 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), + DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(),
The Aspeed SMC device model use to have a 'sdram_base' property. It was removed by commit d177892d4a48 ("aspeed/smc: Remove unused "sdram-base" property") because previous changes simplified the DMA transaction model to use an offset in RAM and not the physical address. The AST2700 SoC has larger address space (64-bit) and a new register DMA DRAM Side Address High Part (0x7C) is introduced to deal with the high bits of the DMA address. To be able to compute the offset of the DMA transaction, as done on the other SoCs, we will need to know where the DRAM is mapped in the address space. Re-introduce a "dram-base" property to hold this value. Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/ssi/aspeed_smc.h | 1 + hw/ssi/aspeed_smc.c | 1 + 2 files changed, 2 insertions(+)