diff mbox series

[06/18] tcg/loongarch64: Simplify tcg_out_dup_vec

Message ID 20240527211912.14060-7-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series tcg/loongarch64: Support v64 and v256 | expand

Commit Message

Richard Henderson May 27, 2024, 9:19 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target.c.inc | 22 ++++++----------------
 1 file changed, 6 insertions(+), 16 deletions(-)

Comments

Philippe Mathieu-Daudé May 29, 2024, 6:34 a.m. UTC | #1 
On 27/5/24 23:19, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-target.c.inc | 22 ++++++----------------
>   1 file changed, 6 insertions(+), 16 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
gaosong June 17, 2024, 9:32 a.m. UTC | #2 
在 2024/5/28 上午5:19, Richard Henderson 写道:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-target.c.inc | 22 ++++++----------------
>   1 file changed, 6 insertions(+), 16 deletions(-)
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 980ea10211..b1d652355d 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1674,22 +1674,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>   static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
>                               TCGReg rd, TCGReg rs)
>   {
> -    switch (vece) {
> -    case MO_8:
> -        tcg_out_opc_vreplgr2vr_b(s, rd, rs);
> -        break;
> -    case MO_16:
> -        tcg_out_opc_vreplgr2vr_h(s, rd, rs);
> -        break;
> -    case MO_32:
> -        tcg_out_opc_vreplgr2vr_w(s, rd, rs);
> -        break;
> -    case MO_64:
> -        tcg_out_opc_vreplgr2vr_d(s, rd, rs);
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> +    static const LoongArchInsn repl_insn[4] = {
> +        OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D
> +    };
> +
> +    tcg_debug_assert(vece <= MO_64);
> +    tcg_out32(s, encode_vdj_insn(repl_insn[vece], rd, rs));
>       return true;
>   }
>
diff mbox series

Patch

diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 980ea10211..b1d652355d 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1674,22 +1674,12 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                             TCGReg rd, TCGReg rs)
 {
-    switch (vece) {
-    case MO_8:
-        tcg_out_opc_vreplgr2vr_b(s, rd, rs);
-        break;
-    case MO_16:
-        tcg_out_opc_vreplgr2vr_h(s, rd, rs);
-        break;
-    case MO_32:
-        tcg_out_opc_vreplgr2vr_w(s, rd, rs);
-        break;
-    case MO_64:
-        tcg_out_opc_vreplgr2vr_d(s, rd, rs);
-        break;
-    default:
-        g_assert_not_reached();
-    }
+    static const LoongArchInsn repl_insn[4] = {
+        OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    tcg_out32(s, encode_vdj_insn(repl_insn[vece], rd, rs));
     return true;
 }