diff mbox series

[08/18] tcg/loongarch64: Support LASX in tcg_out_dupm_vec

Message ID 20240527211912.14060-9-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series tcg/loongarch64: Support v64 and v256 | expand

Commit Message

Richard Henderson May 27, 2024, 9:19 p.m. UTC
Each element size has a different encoding, so code cannot
be shared in the same way as with tcg_out_dup_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target.c.inc | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

Comments

gaosong June 17, 2024, 10:01 a.m. UTC | #1
在 2024/5/28 上午5:19, Richard Henderson 写道:
> Each element size has a different encoding, so code cannot
> be shared in the same way as with tcg_out_dup_vec.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-target.c.inc | 30 ++++++++++++++++++++++++------
>   1 file changed, 24 insertions(+), 6 deletions(-)
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index cc54bc4a53..1e721b8b20 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1690,8 +1690,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
>   static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
>                                TCGReg r, TCGReg base, intptr_t offset)
>   {
> -    /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
> -    if (offset < -0x800 || offset > 0x7ff || \
> +    bool lasx = type == TCG_TYPE_V256;
> +
> +    /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */
> +    if (offset < -0x800 || offset > 0x7ff ||
>           (offset & ((1 << vece) - 1)) != 0) {
>           tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
>           base = TCG_REG_TMP0;
> @@ -1701,16 +1703,32 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
>   
>       switch (vece) {
>       case MO_8:
> -        tcg_out_opc_vldrepl_b(s, r, base, offset);
> +        if (lasx) {
> +            tcg_out_opc_xvldrepl_b(s, r, base, offset);
> +        } else {
> +            tcg_out_opc_vldrepl_b(s, r, base, offset);
> +        }
>           break;
>       case MO_16:
> -        tcg_out_opc_vldrepl_h(s, r, base, offset);
> +        if (lasx) {
> +            tcg_out_opc_xvldrepl_h(s, r, base, offset);
> +        } else {
> +            tcg_out_opc_vldrepl_h(s, r, base, offset);
> +        }
>           break;
>       case MO_32:
> -        tcg_out_opc_vldrepl_w(s, r, base, offset);
> +        if (lasx) {
> +            tcg_out_opc_xvldrepl_w(s, r, base, offset);
> +        } else {
> +            tcg_out_opc_vldrepl_w(s, r, base, offset);
> +        }
>           break;
>       case MO_64:
> -        tcg_out_opc_vldrepl_d(s, r, base, offset);
> +        if (lasx) {
> +            tcg_out_opc_xvldrepl_d(s, r, base, offset);
> +        } else {
> +            tcg_out_opc_vldrepl_d(s, r, base, offset);
> +        }
>           break;
>       default:
>           g_assert_not_reached();
diff mbox series

Patch

diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index cc54bc4a53..1e721b8b20 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1690,8 +1690,10 @@  static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg r, TCGReg base, intptr_t offset)
 {
-    /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
-    if (offset < -0x800 || offset > 0x7ff || \
+    bool lasx = type == TCG_TYPE_V256;
+
+    /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */
+    if (offset < -0x800 || offset > 0x7ff ||
         (offset & ((1 << vece) - 1)) != 0) {
         tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
         base = TCG_REG_TMP0;
@@ -1701,16 +1703,32 @@  static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
 
     switch (vece) {
     case MO_8:
-        tcg_out_opc_vldrepl_b(s, r, base, offset);
+        if (lasx) {
+            tcg_out_opc_xvldrepl_b(s, r, base, offset);
+        } else {
+            tcg_out_opc_vldrepl_b(s, r, base, offset);
+        }
         break;
     case MO_16:
-        tcg_out_opc_vldrepl_h(s, r, base, offset);
+        if (lasx) {
+            tcg_out_opc_xvldrepl_h(s, r, base, offset);
+        } else {
+            tcg_out_opc_vldrepl_h(s, r, base, offset);
+        }
         break;
     case MO_32:
-        tcg_out_opc_vldrepl_w(s, r, base, offset);
+        if (lasx) {
+            tcg_out_opc_xvldrepl_w(s, r, base, offset);
+        } else {
+            tcg_out_opc_vldrepl_w(s, r, base, offset);
+        }
         break;
     case MO_64:
-        tcg_out_opc_vldrepl_d(s, r, base, offset);
+        if (lasx) {
+            tcg_out_opc_xvldrepl_d(s, r, base, offset);
+        } else {
+            tcg_out_opc_vldrepl_d(s, r, base, offset);
+        }
         break;
     default:
         g_assert_not_reached();