| Message ID | 20240529160950.132754-2-rkanwal@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add support for Control Transfer Records Ext. | expand |
On Thu, May 30, 2024 at 2:12 AM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote: > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn32.decode | 1 - > target/riscv/insn_trans/trans_privileged.c.inc | 5 ----- > 2 files changed, 6 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index f22df04cfd..9cb1a1b4ec 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -112,7 +112,6 @@ sret 0001000 00010 00000 000 00000 1110011 > mret 0011000 00010 00000 000 00000 1110011 > wfi 0001000 00101 00000 000 00000 1110011 > sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma > -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > > # *** RV32I Base Instruction Set *** > lui .................... ..... 0110111 @u > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index bc5263a4e0..4eccdddeaa 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -127,8 +127,3 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) > #endif > return false; > } > - > -static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) > -{ > - return false; > -} > -- > 2.34.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f22df04cfd..9cb1a1b4ec 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -112,7 +112,6 @@ sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index bc5263a4e0..4eccdddeaa 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -127,8 +127,3 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) #endif return false; } - -static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) -{ - return false; -}
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 ----- 2 files changed, 6 deletions(-)