From patchwork Fri May 31 12:03:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13681620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3069C27C4F for ; Fri, 31 May 2024 12:09:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sD100-0004Wt-4D; Fri, 31 May 2024 08:04:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sD0zr-0004SB-CJ for qemu-devel@nongnu.org; Fri, 31 May 2024 08:04:35 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sD0zj-0003Uu-Q5 for qemu-devel@nongnu.org; Fri, 31 May 2024 08:04:34 -0400 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-5295eb47b48so2204104e87.1 for ; Fri, 31 May 2024 05:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717157066; x=1717761866; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1DcuS9ybTR6uYgbV5hyqWFCuvELzyzskKa4hioR5OFk=; b=SfUaDseroGeLVWbDRIu9EUy4oGSc9a/1o5GMk5JEz/cIop/Y77OiJtQTrAUCniAclD pIQvmZeZopQVjec4vw4rFNCUfzCBfgOVn8z28CJ7NP2tU6XdN9oDbH1wvgAXy9ahySyW bi5hFbvqKwU5Tfbc/C6gbQjUyx/8cVjR/KJiRRDDZ80C1TY1eM7F7Rju6n9ND3R3X06R P1R5IfvsoU+chGlwx01/lu4gNOhwd9TkoWca8VXT8dfy/bw43YsGQNRJfg2Mdv/v8haJ J8vCSWE2XoN1mklVJq0HKQULd9jeLAvV6wrs5pFfCm0MOoqCEYcs9z1E74PO9JMLYuiH RgOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717157066; x=1717761866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1DcuS9ybTR6uYgbV5hyqWFCuvELzyzskKa4hioR5OFk=; b=n0GeFyPrpy1OVe/feW3nzH5YX8UBrel1r7Kjm3npFflXYfxd7DzFokNDEh1ugmjzG1 CjQrRgZkml23rUyjxivEGYz0cMjiNgXRMhEIlV05/spsJDBQ/br+FqrMY4HQ2byZ1Fof gmXvSmLxC1qGTi1Lnr9Q4W6BUkQ7iuFlPhHw1+90mx/tpnf1ivdIjzcQ7kN9t76lgNw3 K0k2OAshBPn5Yu5QULFzTxa1T0njMHFJpd7/SdNS0iX88iOGPcgcPHv5v4XfKyeaJSWz 64ZFXecZupNrr5jEu5gXBHLG8W+nCejNvd57oEdiBYIuTciKpIajMVCSbNPgfbeoXMAc TqVQ== X-Gm-Message-State: AOJu0Yz0mOEzyMx9UBtWrAFZMDpDpYxu37OZ7yeddZnZCwZluCFWu1BT EE2KPAyPOOoj3bf5oexDmx347v/YEKI9in1osx6eeXqUgzwl4eGlNavhCqDKcMnxu+Bz1i/kmRR d X-Google-Smtp-Source: AGHT+IFe65X7eprrllnjNw7zDT8z0I9yMbiClutKT2w76YKJlOECEWbZ+RbA6NZJCicqzRYDAJis7Q== X-Received: by 2002:ac2:5288:0:b0:51c:348:3ba9 with SMTP id 2adb3069b0e04-52b895879f9mr976021e87.22.1717157065800; Fri, 31 May 2024 05:04:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42129de0cf9sm37027685e9.13.2024.05.31.05.04.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 05:04:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] target/arm: Convert MUL, PMUL to decodetree Date: Fri, 31 May 2024 13:03:51 +0100 Message-Id: <20240531120401.394550-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240531120401.394550-1-peter.maydell@linaro.org> References: <20240531120401.394550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20240528203044.612851-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 5 ++++ target/arm/tcg/translate-a64.c | 51 +++++++++++++--------------------- 2 files changed, 25 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 07b604ec30d..3ea06433701 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -926,6 +926,8 @@ SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e +MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e +PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b ### Advanced SIMD scalar x indexed element @@ -967,3 +969,6 @@ FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h + +MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h +MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 61afbc434fe..1909d1426c4 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5468,6 +5468,8 @@ TRANS(SABA_v, do_gvec_fn3_no64, a, gen_gvec_saba) TRANS(UABA_v, do_gvec_fn3_no64, a, gen_gvec_uaba) TRANS(SABD_v, do_gvec_fn3_no64, a, gen_gvec_sabd) TRANS(UABD_v, do_gvec_fn3_no64, a, gen_gvec_uabd) +TRANS(MUL_v, do_gvec_fn3_no64, a, tcg_gen_gvec_mul) +TRANS(PMUL_v, do_gvec_op3_ool, a, 0, gen_helper_gvec_pmul_b) static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond) { @@ -5694,6 +5696,22 @@ TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true, false) TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true) TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true) +static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a, + gen_helper_gvec_3 * const fns[2]) +{ + assert(a->esz == MO_16 || a->esz == MO_32); + if (fp_access_check(s)) { + gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, a->idx, fns[a->esz - 1]); + } + return true; +} + +static gen_helper_gvec_3 * const f_vector_idx_mul[2] = { + gen_helper_gvec_mul_idx_h, + gen_helper_gvec_mul_idx_s, +}; +TRANS(MUL_vi, do_int3_vector_idx, a, f_vector_idx_mul) + /* * Advanced SIMD scalar pairwise */ @@ -10927,12 +10945,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) int rd = extract32(insn, 0, 5); switch (opcode) { - case 0x13: /* MUL, PMUL */ - if (u && size != 0) { - unallocated_encoding(s); - return; - } - /* fall through */ case 0x12: /* MLA, MLS */ if (size == 3) { unallocated_encoding(s); @@ -10969,6 +10981,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0x0f: /* SABA, UABA */ case 0x10: /* ADD, SUB */ case 0x11: /* CMTST, CMEQ */ + case 0x13: /* MUL, PMUL */ unallocated_encoding(s); return; } @@ -10978,13 +10991,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { - case 0x13: /* MUL, PMUL */ - if (!u) { /* MUL */ - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); - } else { /* PMUL */ - gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b); - } - return; case 0x12: /* MLA, MLS */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size); @@ -12198,7 +12204,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) TCGv_ptr fpst; switch (16 * u + opcode) { - case 0x08: /* MUL */ case 0x10: /* MLA */ case 0x14: /* MLS */ if (is_scalar) { @@ -12285,6 +12290,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x01: /* FMLA */ case 0x04: /* FMLSL */ case 0x05: /* FMLS */ + case 0x08: /* MUL */ case 0x09: /* FMUL */ case 0x18: /* FMLAL2 */ case 0x19: /* FMULX */ @@ -12407,22 +12413,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } return; - case 0x08: /* MUL */ - if (!is_long && !is_scalar) { - static gen_helper_gvec_3 * const fns[3] = { - gen_helper_gvec_mul_idx_h, - gen_helper_gvec_mul_idx_s, - gen_helper_gvec_mul_idx_d, - }; - tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), - vec_full_reg_offset(s, rn), - vec_full_reg_offset(s, rm), - is_q ? 16 : 8, vec_full_reg_size(s), - index, fns[size - 1]); - return; - } - break; - case 0x10: /* MLA */ if (!is_long && !is_scalar) { static gen_helper_gvec_4 * const fns[3] = { @@ -12491,7 +12481,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); switch (16 * u + opcode) { - case 0x08: /* MUL */ case 0x10: /* MLA */ case 0x14: /* MLS */ {