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Mon, 3 Jun 2024 05:59:53 +0000 From: CLEMENT MATHIEU--DRIF To: "qemu-devel@nongnu.org" CC: "jasowang@redhat.com" , "zhenzhong.duan@intel.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "joao.m.martins@oracle.com" , "peterx@redhat.com" , "mst@redhat.com" , CLEMENT MATHIEU--DRIF Subject: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS Thread-Topic: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS Thread-Index: AQHatXtBWfzK4X3MW0619Cac8t7GQQ== Date: Mon, 3 Jun 2024 05:59:53 +0000 Message-ID: <20240603055917.18735-21-clement.mathieu--drif@eviden.com> References: <20240603055917.18735-1-clement.mathieu--drif@eviden.com> In-Reply-To: <20240603055917.18735-1-clement.mathieu--drif@eviden.com> Accept-Language: en-GB, fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=eviden.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: AM8PR07MB7602:EE_|AM8PR07MB8192:EE_ x-ms-office365-filtering-correlation-id: dc3b9bbd-e9a1-4fb1-addd-08dc8392638d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 44 +++++++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 52 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 0e14ef4ab2..10b0708130 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2833,6 +2833,50 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } +ssize_t pci_ats_request_translation_pasid(PCIDevice *dev, uint32_t pasid, + bool priv_req, bool exec_req, hwaddr addr, + size_t length, bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count) +{ + assert(result_length); + IOMMUMemoryRegion *iommu_mr = pci_device_iommu_memory_region_pasid(dev, + pasid); + if (!iommu_mr || !pcie_ats_enabled(dev)) { + return -EPERM; + } + return memory_region_iommu_ats_request_translation(iommu_mr, priv_req, + exec_req, addr, length, + no_write, result, + result_length, + err_count); +} + +int pci_register_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n) +{ + IOMMUMemoryRegion *iommu_mr = pci_device_iommu_memory_region_pasid(dev, + pasid); + if (!iommu_mr) { + return -EPERM; + } + return memory_region_register_iommu_notifier(MEMORY_REGION(iommu_mr), n, + &error_fatal); +} + +int pci_unregister_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n) +{ + IOMMUMemoryRegion *iommu_mr = pci_device_iommu_memory_region_pasid(dev, + pasid); + if (!iommu_mr) { + return -EPERM; + } + memory_region_unregister_iommu_notifier(MEMORY_REGION(iommu_mr), n); + return 0; +} + void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque) { /* diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 2147981423..8adba6af97 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -473,6 +473,58 @@ bool pci_iommu_init_iotlb_notifier(PCIDevice *dev, uint32_t pasid, IOMMUNotifier *n, IOMMUNotify fn, void* opaque); +/** + * pci_ats_request_translation_pasid: perform an ATS request + * + * Return the number of translations stored in @result in case of success, + * a negative error code otherwise. + * -ENOMEM is returned when the result buffer is not large enough to store + * all the translations + * + * @dev: the ATS-capable PCI device + * @pasid: the pasid of the address space in which the translation will be made + * @priv_req: privileged mode bit (PASID TLP) + * @exec_req: execute request bit (PASID TLP) + * @addr: start address of the memory range to be translated + * @length: length of the memory range in bytes + * @no_write: request a read-only access translation (if supported by the IOMMU) + * @result: buffer in which the TLB entries will be stored + * @result_length: result buffer length + * @err_count: number of untranslated subregions + */ +ssize_t pci_ats_request_translation_pasid(PCIDevice *dev, uint32_t pasid, + bool priv_req, bool exec_req, hwaddr addr, + size_t length, bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count); + +/** + * pci_register_iommu_tlb_event_notifier: register a notifier for changes to + * IOMMU translation entries in a specific address space. + * + * Returns 0 on success, or a negative errno otherwise. + * + * @dev: the device that wants to get notified + * @pasid: the pasid of the address space to track + * @n: the notifier to register + */ +int pci_register_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n); + +/** + * pci_unregister_iommu_tlb_event_notifier: unregister a notifier that has been + * registerd with pci_register_iommu_tlb_event_notifier + * + * Returns 0 on success, or a negative errno otherwise. + * + * @dev: the device that wants to unsubscribe + * @pasid: the pasid of the address space to be untracked + * @n: the notifier to unregister + */ +int pci_unregister_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n); + /** * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus *