Message ID | 20240603111643.258712-1-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Hi Alistair, On 3/6/24 13:16, Alistair Francis wrote: > The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184: > > Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603 > > for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de: > > disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.1 > > * APLICs add child earlier than realize > * Fix exposure of Zkr > * Raise exceptions on wrs.nto > * Implement SBI debug console (DBCN) calls for KVM > * Support 64-bit addresses for initrd > * Change RISCV_EXCP_SEMIHOST exception number to 63 > * Tolerate KVM disable ext errors > * Set tval in breakpoints > * Add support for Zve32x extension > * Add support for Zve64x extension > * Relax vector register check in RISCV gdbstub > * Fix the element agnostic Vector function problem > * Fix Zvkb extension config > * Implement dynamic establishment of custom decoder > * Add th.sxstatus CSR emulation > * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions > * Check single width operator for vector fp widen instructions > * Check single width operator for vfncvt.rod.f.f.w > * Remove redudant SEW checking for vector fp narrow/widen instructions > * Prioritize pmp errors in raise_mmu_exception() > * Do not set mtval2 for non guest-page faults > * Remove experimental prefix from "B" extension > * Fixup CBO extension register calculation > * Fix the hart bit setting of AIA > * Fix reg_width in ricsv_gen_dynamic_vector_feature() > * Decode all of the pmpcfg and pmpaddr CSRs > > ---------------------------------------------------------------- Please have a look at this bugfix: https://lore.kernel.org/qemu-devel/20240419110514.69697-1-philmd@linaro.org/
On 6/3/24 06:16, Alistair Francis wrote: > The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184: > > Merge tag 'pull-target-arm-20240531' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603 > > for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de: > > disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.1 > > * APLICs add child earlier than realize > * Fix exposure of Zkr > * Raise exceptions on wrs.nto > * Implement SBI debug console (DBCN) calls for KVM > * Support 64-bit addresses for initrd > * Change RISCV_EXCP_SEMIHOST exception number to 63 > * Tolerate KVM disable ext errors > * Set tval in breakpoints > * Add support for Zve32x extension > * Add support for Zve64x extension > * Relax vector register check in RISCV gdbstub > * Fix the element agnostic Vector function problem > * Fix Zvkb extension config > * Implement dynamic establishment of custom decoder > * Add th.sxstatus CSR emulation > * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions > * Check single width operator for vector fp widen instructions > * Check single width operator for vfncvt.rod.f.f.w > * Remove redudant SEW checking for vector fp narrow/widen instructions > * Prioritize pmp errors in raise_mmu_exception() > * Do not set mtval2 for non guest-page faults > * Remove experimental prefix from "B" extension > * Fixup CBO extension register calculation > * Fix the hart bit setting of AIA > * Fix reg_width in ricsv_gen_dynamic_vector_feature() > * Decode all of the pmpcfg and pmpaddr CSRs Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~