[PULL,v2,18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions

From: Max Chou <max.chou@sifive.com>

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Max Chou <max.chou@sifive.com>,
 Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 qemu-stable <qemu-stable@nongnu.org>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 18/27] target/riscv: rvv: Check single width operator for
 vector fp widen instructions
Date: Mon,  3 Jun 2024 21:16:34 +1000
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Message ID	20240603111643.258712-19-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou <max.chou@sifive.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, qemu-stable <qemu-stable@nongnu.org>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions Date: Mon, 3 Jun 2024 21:16:34 +1000 Message-ID: <20240603111643.258712-19-alistair.francis@wdc.com> In-Reply-To: <20240603111643.258712-1-alistair.francis@wdc.com> References: <20240603111643.258712-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/27] hw/intc/riscv_aplic: APLICs should add child earlier than realize \| expand [PULL,v2,01/27] hw/intc/riscv_aplic: APLICs should add child earlier than realize [PULL,v2,02/27] target/riscv/kvm: Fix exposure of Zkr [PULL,v2,03/27] target/riscv: Raise exceptions on wrs.nto [PULL,v2,04/27] target/riscv/kvm: implement SBI debug console (DBCN) calls [PULL,v2,05/27] hw/riscv/boot.c: Support 64-bit address for initrd [PULL,v2,06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 [PULL,v2,07/27] target/riscv/kvm: tolerate KVM disable ext errors [PULL,v2,08/27] target/riscv/debug: set tval=pc in breakpoint exceptions [PULL,v2,09/27] trans_privileged.c.inc: set (m\|s)tval on ebreak breakpoint [PULL,v2,10/27] target/riscv: Add support for Zve32x extension [PULL,v2,11/27] target/riscv: Add support for Zve64x extension [PULL,v2,12/27] target/riscv: Relax vector register check in RISCV gdbstub [PULL,v2,13/27] target/riscv: Fix the element agnostic function problem [PULL,v2,14/27] target/riscv/cpu.c: fix Zvkb extension config [PULL,v2,15/27] target/riscv: Implement dynamic establishment of custom decoder [PULL,v2,16/27] riscv: thead: Add th.sxstatus CSR emulation [PULL,v2,17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructi… [PULL,v2,18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions [PULL,v2,19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w [PULL,v2,20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instruct… [PULL,v2,21/27] target/riscv: prioritize pmp errors in raise_mmu_exception() [PULL,v2,22/27] target/riscv: do not set mtval2 for non guest-page faults [PULL,v2,23/27] target/riscv: Remove experimental prefix from "B" extension [PULL,v2,24/27] target/riscv: rvzicbo: Fixup CBO extension register calculation [PULL,v2,25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA [PULL,v2,26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() [PULL,v2,27/27] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

[PULL,v2,18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions

Commit Message

Patch