| Message ID | 20240604062747.9212-3-fea.wang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Support RISC-V privilege 1.13 spec | expand |
On Tue, Jun 4, 2024 at 4:23 PM Fea.Wang <fea.wang@sifive.com> wrote: > > Add macros and variables for RISC-V privilege 1.13 support. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Weiwei Li <liwei1518@gmail.com> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 4 +++- > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 94600b91fa..4d73486ea2 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; > #define PRIV_VER_1_10_0_STR "v1.10.0" > #define PRIV_VER_1_11_0_STR "v1.11.0" > #define PRIV_VER_1_12_0_STR "v1.12.0" > +#define PRIV_VER_1_13_0_STR "v1.13.0" > enum { > PRIV_VERSION_1_10_0 = 0, > PRIV_VERSION_1_11_0, > PRIV_VERSION_1_12_0, > + PRIV_VERSION_1_13_0, > > - PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, > + PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, > }; > > #define VEXT_VERSION_1_00_0 0x00010000 > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index e1e4f32698..fb7eebde52 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -136,6 +136,7 @@ struct RISCVCPUConfig { > * TCG always implement/can't be user disabled, > * based on spec version. > */ > + bool has_priv_1_13; > bool has_priv_1_12; > bool has_priv_1_11; > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 94600b91fa..4d73486ea2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_12_0_STR "v1.12.0" +#define PRIV_VER_1_13_0_STR "v1.13.0" enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + PRIV_VERSION_1_13_0, - PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, + PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, }; #define VEXT_VERSION_1_00_0 0x00010000 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..fb7eebde52 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,6 +136,7 @@ struct RISCVCPUConfig { * TCG always implement/can't be user disabled, * based on spec version. */ + bool has_priv_1_13; bool has_priv_1_12; bool has_priv_1_11;