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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:44 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Date: Tue, 4 Jun 2024 14:27:45 +0800 Message-Id: <20240604062747.9212-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..28bd3fb0b4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -315,6 +315,7 @@ #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) +#define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58ef7079dc..3dcfb343fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2245,6 +2245,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2280,6 +2284,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateenh(env, csrno, wr_mask, new_val); }