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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH v2 06/10] target/s390x: Use deposit in save_link_info Date: Wed, 5 Jun 2024 14:57:35 -0700 Message-Id: <20240605215739.4758-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace manual masking and oring with deposits. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2654c85a8e..0f0688424f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1418,24 +1418,32 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) static void save_link_info(DisasContext *s, DisasOps *o) { - TCGv_i64 t; + TCGv_i64 t1, t2; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { pc_to_link_info(o->out, s); return; } + gen_op_calc_cc(s); - t = tcg_temp_new_i64(); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - gen_psw_addr_disp(s, t, s->ilen); - tcg_gen_or_i64(o->out, o->out, t); - tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); - tcg_gen_shri_i64(t, psw_mask, 16); - tcg_gen_andi_i64(t, t, 0x0f000000); - tcg_gen_or_i64(o->out, o->out, t); - tcg_gen_extu_i32_i64(t, cc_op); - tcg_gen_shli_i64(t, t, 28); - tcg_gen_or_i64(o->out, o->out, t); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + /* Shift program mask into place, garbage outside of [27:24]. */ + tcg_gen_shri_i64(t1, psw_mask, 16); + /* Deposit pc to replace garbage bits below program mask. */ + gen_psw_addr_disp(s, t2, s->ilen); + tcg_gen_deposit_i64(t1, t1, t2, 0, 24); + /* + * Deposit cc to replace garbage bits above program mask. + * Note that cc is in [0-3], thus [63:30] are set to zero. + */ + tcg_gen_extu_i32_i64(t2, cc_op); + tcg_gen_deposit_i64(t1, t1, t2, 28, 64 - 28); + /* Install ilen. */ + tcg_gen_ori_i64(t1, t1, (s->ilen / 2) << 30); + + tcg_gen_deposit_i64(o->out, o->out, t1, 0, 32); } static DisasJumpType op_bal(DisasContext *s, DisasOps *o)