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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either 1 or CL - and therefore decode->op[2] is taken by the low part of the register being shifted. Pass X86_OP_* to gen_shift_count from its current callers and hardcode cpu_regs[R_ECX] as the shift count. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/emit.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 41398e5130c..2e73b41cd3e 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2998,16 +2998,16 @@ static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode) } static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, - bool *can_be_zero, TCGv *count) + bool *can_be_zero, TCGv *count, int unit) { MemOp ot = decode->op[0].ot; int mask = (ot <= MO_32 ? 0x1f : 0x3f); *can_be_zero = false; - switch (decode->op[2].unit) { + switch (unit) { case X86_OP_INT: *count = tcg_temp_new(); - tcg_gen_andi_tl(*count, s->T1, mask); + tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask); *can_be_zero = true; break; @@ -3192,7 +3192,7 @@ static void gen_RCL(DisasContext *s, X86DecodedInsn *decode) bool have_1bit_cin, can_be_zero; TCGv count; TCGLabel *zero_label = NULL; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv low, high, low_count; if (!count) { @@ -3244,7 +3244,7 @@ static void gen_RCR(DisasContext *s, X86DecodedInsn *decode) bool have_1bit_cin, can_be_zero; TCGv count; TCGLabel *zero_label = NULL; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv low, high, high_count; if (!count) { @@ -3422,7 +3422,7 @@ static void gen_ROL(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv_i32 temp32, count32; TCGv old = tcg_temp_new(); @@ -3450,7 +3450,7 @@ static void gen_ROR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv_i32 temp32, count32; TCGv old = tcg_temp_new(); @@ -3562,7 +3562,7 @@ static void gen_SAR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return; @@ -3690,7 +3690,7 @@ static void gen_SHL(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return; @@ -3722,7 +3722,7 @@ static void gen_SHR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return;