diff mbox series

[22/25] target/i386: list instructions still in translate.c

Message ID 20240608084113.2770363-23-pbonzini@redhat.com (mailing list archive)
State New, archived
Headers show
Series target/i386: more progress towards new decoder | expand

Commit Message

Paolo Bonzini June 8, 2024, 8:41 a.m. UTC
Group them so that it is easier to figure out which two-byte opcodes to
tackle together.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/decode-new.c.inc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Richard Henderson June 8, 2024, 8:14 p.m. UTC | #1
On 6/8/24 01:41, Paolo Bonzini wrote:
> Group them so that it is easier to figure out which two-byte opcodes to
> tackle together.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/tcg/decode-new.c.inc | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index d75d242e552..7463cf87f1a 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -129,6 +129,24 @@ 
  *
  *    (^)  these are the two cases in which Intel and AMD disagree on the
  *         primary exception class
+ *
+ * Instructions still in translate.c
+ * ---------------------------------
+ * x87:
+ * 0xD8 - 0xDF
+ *
+ * privileged/system:
+ * 0x0F 0x00              group 6 (SLDT, STR, LLDT, LTR, VERR, VERW)
+ * 0x0F 0x01              group 7 (SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, INVLPG,
+ *                                 MONITOR, MWAIT, CLAC, STAC, XGETBV, XSETBV,
+ *                                 SWAPGS, RDTSCP)
+ *
+ * MPX:
+ * 0x0F 0x1A              BNDLDX, BNDMOV, BNDCL, BNDCU
+ * 0x0F 0x1B              BNDSTX, BNDMOV, BNDMK, BNDCN
+
+ * integer ops - atomic:
+ * 0x0F 0xC7              group 9 (CMPXCHG8B/CMPXCHG16B; also RDRAND, RDSEED, RDPID)
  */
 
 #define X86_OP_NONE { 0 },