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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a bit more generic, as it can be applied to MPX as well. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/decode-new.h | 5 +++-- target/i386/tcg/decode-new.c.inc | 12 ++++-------- target/i386/tcg/emit.c.inc | 3 ++- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index f704698575f..46a96b220d0 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -170,8 +170,9 @@ typedef enum X86InsnSpecial { /* Always locked if it has a memory operand (XCHG) */ X86_SPECIAL_Locked, - /* Do not apply segment base to effective address */ - X86_SPECIAL_NoSeg, + /* Do not load effective address in s->A0 */ + X86_SPECIAL_NoLoadEA, + /* * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits * (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index d41002e2f5c..4f5fcdb88dd 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -193,7 +193,7 @@ X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__) #define cpuid(feat) .cpuid = X86_FEAT_##feat, -#define noseg .special = X86_SPECIAL_NoSeg, +#define nolea .special = X86_SPECIAL_NoLoadEA, #define xchg .special = X86_SPECIAL_Locked, #define lock .special = X86_SPECIAL_HasLock, #define mmx .special = X86_SPECIAL_MMX, @@ -1592,7 +1592,7 @@ static const X86OpEntry opcodes_root[256] = { [0x8B] = X86_OP_ENTRYwr(MOV, G,v, E,v), /* Missing in Table A-2: memory destination is always 16-bit. */ [0x8C] = X86_OP_ENTRYwr(MOV, E,v, S,w, op0_Mw), - [0x8D] = X86_OP_ENTRYwr(LEA, G,v, M,v, noseg), + [0x8D] = X86_OP_ENTRYwr(LEA, G,v, M,v, nolea), [0x8E] = X86_OP_ENTRYwr(MOV, S,w, E,w), [0x8F] = X86_OP_GROUPw(group1A, E,v), @@ -2524,11 +2524,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu) assert(decode.op[1].unit == X86_OP_INT); break; - case X86_SPECIAL_NoSeg: - decode.mem.def_seg = -1; - s->override = -1; - break; - case X86_SPECIAL_Op0_Mw: assert(decode.op[0].unit == X86_OP_INT); if (decode.op[0].has_ea) { @@ -2585,7 +2580,8 @@ static void disas_insn(DisasContext *s, CPUState *cpu) gen_helper_enter_mmx(tcg_env); } - if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) { + if (decode.e.special != X86_SPECIAL_NoLoadEA && + (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea)) { gen_load_ea(s, &decode.mem, decode.e.vex_class == 12); } if (s->prefix & PREFIX_LOCK) { diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 78d89db57cd..e6521632edd 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1970,7 +1970,8 @@ static void gen_LDS(DisasContext *s, X86DecodedInsn *decode) static void gen_LEA(DisasContext *s, X86DecodedInsn *decode) { - tcg_gen_mov_tl(s->T0, s->A0); + TCGv ea = gen_lea_modrm_1(s, decode->mem, false); + gen_lea_v_seg_dest(s, s->aflag, s->T0, ea, -1, -1); } static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode)