| Message ID | 20240616024657.17948-2-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce extension implied rules | expand |
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote: > From: Frank Chang <frank.chang@sifive.com> > > RISCVCPUImpliedExtsRule is created to store the implied rules. > 'is_misa' flag is used to distinguish whether the rule is derived > from the MISA or other extensions. > 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores > the offset of the extension defined in RISCVCPUConfig. 'ext' will also > serve as the key of the hash tables to look up the rule in the following > commit. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> > Tested-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 8 ++++++++ > target/riscv/cpu.h | 25 +++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4760cb2cc1..bacbb32120 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] = { > NULL, > }; > > +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = { > + NULL > +}; > + > +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = { > + NULL > +}; > + > static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 90b8f1b08f..6b31731fa8 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -124,6 +124,31 @@ typedef enum { > EXT_STATUS_DIRTY, > } RISCVExtStatus; > > +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule; > + > +struct riscv_cpu_implied_exts_rule { > +#ifndef CONFIG_USER_ONLY > + /* > + * Bitmask indicates the rule enabled status for the harts. > + * This enhancement is only available in system-mode QEMU, > + * as we don't have a good way (e.g. mhartid) to distinguish > + * the SMP cores in user-mode QEMU. > + */ > + uint64_t enabled; > +#endif > + /* True if this is a MISA implied rule. */ > + bool is_misa; > + /* ext is MISA bit if is_misa flag is true, else extension offset. */ > + const uint32_t ext; > + const uint32_t implied_misas; > + const uint32_t implied_exts[]; > +}; > + > +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[]; > +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[]; > + > +#define RISCV_IMPLIED_EXTS_RULE_END -1 > + > #define MMU_USER_IDX 3 > > #define MAX_RISCV_PMPS (16)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4760cb2cc1..bacbb32120 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] = { NULL, }; +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = { + NULL +}; + +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = { + NULL +}; + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b8f1b08f..6b31731fa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -124,6 +124,31 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule; + +struct riscv_cpu_implied_exts_rule { +#ifndef CONFIG_USER_ONLY + /* + * Bitmask indicates the rule enabled status for the harts. + * This enhancement is only available in system-mode QEMU, + * as we don't have a good way (e.g. mhartid) to distinguish + * the SMP cores in user-mode QEMU. + */ + uint64_t enabled; +#endif + /* True if this is a MISA implied rule. */ + bool is_misa; + /* ext is MISA bit if is_misa flag is true, else extension offset. */ + const uint32_t ext; + const uint32_t implied_misas; + const uint32_t implied_exts[]; +}; + +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[]; +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[]; + +#define RISCV_IMPLIED_EXTS_RULE_END -1 + #define MMU_USER_IDX 3 #define MAX_RISCV_PMPS (16)