[v2,3/6] target/riscv: Add MISA implied rules

Commit Message

Frank Chang June 16, 2024, 2:46 a.m. UTC

From: Frank Chang <[e-mail]>

Add MISA extension implied rules to enable the implied extensions
of MISA recursively.

Signed-off-by: Frank Chang <[e-mail]>
Reviewed-by: Jerry Zhang Jian <[e-mail]>
Tested-by: Max Chou <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
---
 target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

Comments

Daniel Henrique Barboza June 20, 2024, 7:53 p.m. UTC | #1

On 6/15/24 11:46 PM, [e-mail] wrote:
> From: Frank Chang <[e-mail]>
> 
> Add MISA extension implied rules to enable the implied extensions
> of MISA recursively.
> 
> Signed-off-by: Frank Chang <[e-mail]>
> Reviewed-by: Jerry Zhang Jian <[e-mail]>
> Tested-by: Max Chou <[e-mail]>
> Reviewed-by: Alistair Francis <[e-mail]>
> ---

Reviewed-by: Daniel Henrique Barboza <[e-mail]>

>   target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bacbb32120..d09b5e9e62 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] = {
>       NULL,
>   };
>   
> +static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVA,
> +    .implied_exts = {
> +        CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVD,
> +    .implied_misas = RVF,
> +    .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVF,
> +    .implied_exts = {
> +        CPU_CFG_OFFSET(ext_zicsr),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVM,
> +    .implied_exts = {
> +        CPU_CFG_OFFSET(ext_zmmul),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVV,
> +    .implied_exts = {
> +        CPU_CFG_OFFSET(ext_zve64d),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> -    NULL
> +    &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> +    &RVM_IMPLIED, &RVV_IMPLIED, NULL
>   };
>   
>   RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bacbb32120..d09b5e9e62 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2250,8 +2250,56 @@  RISCVCPUProfile *riscv_profiles[] = {
     NULL,
 };
 
+static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
+    .is_misa = true,
+    .ext = RVA,
+    .implied_exts = {
+        CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
+    .is_misa = true,
+    .ext = RVD,
+    .implied_misas = RVF,
+    .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
+    .is_misa = true,
+    .ext = RVF,
+    .implied_exts = {
+        CPU_CFG_OFFSET(ext_zicsr),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
+    .is_misa = true,
+    .ext = RVM,
+    .implied_exts = {
+        CPU_CFG_OFFSET(ext_zmmul),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
+    .is_misa = true,
+    .ext = RVV,
+    .implied_exts = {
+        CPU_CFG_OFFSET(ext_zve64d),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
-    NULL
+    &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
+    &RVM_IMPLIED, &RVV_IMPLIED, NULL
 };
 
 RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {