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Iglesias'" , Peter Maydell , , "Edgar E . Iglesias" Subject: [PATCH v3 1/3] hw/misc/zynq_slcr: Add boot-mode property Date: Thu, 20 Jun 2024 16:11:37 +0530 Message-ID: <20240620104139.217908-2-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240620104139.217908-1-sai.pavan.boddu@amd.com> References: <20240620104139.217908-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|PH7PR12MB7818:EE_ X-MS-Office365-Filtering-Correlation-Id: 661a38b3-3bdd-4201-bde8-08dc91159895 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|1800799021|82310400023|36860700010|376011; X-Microsoft-Antispam-Message-Info: M0rzBIpGCAIeYfsPU9oYhG7pKnE1bUGmZeYVYgGD/uLUefo7VBnwVRLpJuP/babykBshBPy6rbVa7CZepe2cft98RLqQ6QjmgYPlzTheACM6n6c4RPds+0NLc6Mg/tanRo3sE1l+gXqfzG/bcumsFkeTEHG2Oh+WI2BOqWzVdJBhnZCIpDTITqNMQOjBBmi2nnmXKbwAMlgA81v0hJ1apHix1fVqpkByh8XA+lQws3qLL3itjVepkM9KOOCdH0XxTUAhltQWX+hzGR914kaazhE9tKgI6CfPGYckhy4a+evjZ9KBXYAdqEMkLjGdmpkIfQvhGoFS03Isi4E3G3w2eWBdtWCuEYBh8zcDFzLFje4uVr5QUTOjkFXYTLdjFoCiTnxXyQbUiegPG/wn55D3vZJYFc2JQ0JRQN5k+H1Z9Hr32X8Cd07OuAAXGCC++uNKZaaGLzdpF+gyugkO8f679EMLH8Rl5PN793ZhmGOR21FGNPofXxI8SVTLBUHOy30czNVxfo0TkhY/JV3bhXf5zZYK9qRqiTdoGG8bLEEXrYpC4VbgnsV76n56RCv5RtWrHY8ZzjJdyX5U/eVJiBpLVfdjVa90bijAScAa6xlzHqQltTqMQmCuM4MowqTN0/WJ5+FsyB81UCRNWIsB6C6OFVVAq4abIaGXyKPW5hnIIx6O/E92HmZ7aJIj/+68hvcIxsPWOk7TNfl2bTGEnTlbXBmKkTpzUAk6oPq2mjzVy23khhq5Wb4ES/SjPRkHFdenSumTa30ucUjgdzO0FppUEuC0S4u6DedfZL2qbH+J45ksYxVxIH5/PfOAu4y3iWFXGjObEC2/7108DmwNneqaVwsGPtdvXwSpKTVOeIE7TLGZuFJ4CaT5zf1x10ufahayJDzZ7AKUNwc+BS7eNDlJu3cTovoFr0a5yrR+kP8gqFpkANvSka5wso72puqHPkarnN1iA0jv5JHvaAINB0QFlbPAiDLs36HZnnAhdP+T6alDuEVWAlnrMmPEDzHtG6fNH1pz1e554w8zBtDMDe/rwAPofZJKAJSOw0984EE04c47U+njaChx0q38KgTs9JAfGs94QjkQ8pu13EIDSeuaXxkR0p6MDoWZ7v1Oq5GoRnMvEC1AT+OukM5sFuJPwZ5ITZ2t7AMd1TZCZYVfGBlJUjgRxvUT7bBihwC8ASkvfHQEMvTNaccezW6jKhxnD0sMQkSr2VnYqlBAxrA7PEFXf4OgXVo8L0Je1xw4UZEK2Kl3HbXgFQ34WUaimMCFusrmALhsxXTuZz+08F4cbc91uAYCbdXfsax6N6qUKoTNrsKHly286v7wqQ/yS7uaG3198bcheihwhA36LJU09vxqLKzvS9eGqWNb7xl8PEPF7qA9IMRdqxKy+Lj5FaDkm6NHBiTCDG9o2QEStnaKcHby2w== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(1800799021)(82310400023)(36860700010)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2024 10:41:51.8340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 661a38b3-3bdd-4201-bde8-08dc91159895 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7818 Received-SPF: permerror client-ip=2a01:111:f403:2414::625; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org boot-mode property sets user values into BOOT_MODE register, on hardware these are derived from board switches. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; s->regs[R_RST_REASON] = 0x00000040; - s->regs[R_BOOT_MODE] = 0x00000001; + s->regs[R_BOOT_MODE] = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK; /* 0x700 - 0x7D4 */ for (i = 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks = { QDEV_CLOCK_END }; +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s = ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr = { } }; +static Property zynq_slcr_props[] = { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); dc->vmsd = &vmstate_zynq_slcr; + dc->realize = zynq_slcr_realize; rc->phases.enter = zynq_slcr_reset_init; rc->phases.hold = zynq_slcr_reset_hold; rc->phases.exit = zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } static const TypeInfo zynq_slcr_info = {