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Iglesias'" , Peter Maydell , , , "Edgar E . Iglesias" Subject: [PATCH v4 1/3] hw/misc/zynq_slcr: Add boot-mode property Date: Fri, 21 Jun 2024 18:29:04 +0530 Message-ID: <20240621125906.1300995-2-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> References: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|PH8PR12MB7206:EE_ X-MS-Office365-Filtering-Correlation-Id: c052f004-7ccc-46b5-ebad-08dc91f1f7bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|82310400023|36860700010|1800799021|376011; X-Microsoft-Antispam-Message-Info: 3G9CSf9+n7ffGXgRq6P6MQYPlC31bOvnrMecGQ1c45N1/f1ytfWXbVUiThTHMxEaAfN0qQN7WRgMIkWOjA2YtYAHOFJrOKw3KzaAuZaWXse7rEIziN0tHBgsFgf/xv5SthHfquVilBnoENsHXeEtyyg93bfrRg1ef0b4V898YMH6e6RB7lrSlIz+VO2Lwouq5CWnjtraKd67OH0VhgzVo7PQT6VXazf/UZqMEJV+2f/2wRHpNXZW54ztaCG3Y3QQTqXkZAjUqxanhcyiO/k0L4BhhxGbTlnfA4xXBfwG9gYy7Kwq0DKGvq9NbpAad6nSFtZIGtUpjI8k7gXBuIhLuCVd1eNrApzfThlLF5SEAbBdzlhIDKgzwX4SZE8ND9vEMpZx1nBolhYPOYmbUZ56vH0Qw2gpdSACuJoSmvGQYOnqWZlwMSF+fJBKtS1nh8yKfj3x7D6QCky+hvDLZNSa8LNMqS7RbOGjLVVl6CthuvOhBVJU+G2KDnHwCXbVVN7V72nsiBIlz6SpzE25fJNe4hhGokAoq+i38z1lbzmQCjsQImU5050vGQNYdQiJ86dAblKIRfVqAOkzEILt5LF2ViDFPgIuOdhtWuzeEqxSWuxvGxUTTzzlPAGzPTaa89qlfPCKfjfP1CU7fG2b/qFZ3j27OludwIMQbnYa65BWmN/1yg42vkgGKxqXDTDgkN4AaVM7Jd9Wc11N7OU9/7ydfgcqZgmlcNPtr9p35gQJ3nS0qCaH4v73bL70AatnggSwb9jzW6qgLCrP6I1GiCtRS7Lk4OGbATmnBxPGqdcWW/MP6Rl9NG/ndwxFT6tXsOjpX2Dyq6mFmrf66D+TP5/TUa+RxDtAlLrULhRdJ3SKMof4dJHU+Kwvy86nvxB34kB9usBgDfItowdcu+NnwMtC8o6s0Ihe3aSLb/PT5vLYKU6uTomfjsCTjI226tw5rubVo1OlRwkO+0pdJ5FUAmzMa2gXY+NhZVAL+d7l3MMth1JOA5y/K40oz1Ql3Y6+a2B7JhAqI0QaSD78aiDDa2ax1c/QP25wCbmZVY6iyi47qUDi7YpdMheiAlRxyyExPZjqJ6yw0XxCskYI+udNT1s4rmW0BxM0bm8HQkyvPBY/MPW7QkauooBkv1fYFQOr6yB99PARTLKhH2wYhNBX8Tf9WyzXh1FePihf6QcIR+Ksajj5MtJKMhr0IgzTGRzGlJviAK3yig6Axa+Jo37LXFKTyG36zi339TOjqjthN+mBiJChbVJmaQZHKwIfCy4g5LHsNR7s69emYlT5nVB46O7Kk6KMKJ/yimIksea6fDQhPBL1wKQ/8/A+CBoVzfSyDS/gh93ZJiuU+HD3rvUedu83R2JI8iK2FoGELUUd7G5b6AsbJ33XY7BOpJzrAS6NEWFOT1RoCBLIFEVGAxdjqWi/AQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(82310400023)(36860700010)(1800799021)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 12:59:20.3576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c052f004-7ccc-46b5-ebad-08dc91f1f7bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7206 Received-SPF: permerror client-ip=2a01:111:f403:2414::615; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org boot-mode property sets user values into BOOT_MODE register, on hardware these are derived from board switches. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; s->regs[R_RST_REASON] = 0x00000040; - s->regs[R_BOOT_MODE] = 0x00000001; + s->regs[R_BOOT_MODE] = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK; /* 0x700 - 0x7D4 */ for (i = 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks = { QDEV_CLOCK_END }; +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s = ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr = { } }; +static Property zynq_slcr_props[] = { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); dc->vmsd = &vmstate_zynq_slcr; + dc->realize = zynq_slcr_realize; rc->phases.enter = zynq_slcr_reset_init; rc->phases.hold = zynq_slcr_reset_hold; rc->phases.exit = zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } static const TypeInfo zynq_slcr_info = {