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Iglesias'" , Peter Maydell , , , "Edgar E . Iglesias" Subject: [PATCH v4 2/3] hw/arm/xilinx_zynq: Add boot-mode property Date: Fri, 21 Jun 2024 18:29:05 +0530 Message-ID: <20240621125906.1300995-3-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> References: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|MW4PR12MB5642:EE_ X-MS-Office365-Filtering-Correlation-Id: 184162ac-68e3-45ab-48ee-08dc91f1f912 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|376011|36860700010|1800799021|82310400023; X-Microsoft-Antispam-Message-Info: qp+orFz4vMuETUekul6yznNpampYvMbRAVGJxYo/rq3Dqt34boMQ7RSIXkae9ptiQnGBQ9o8oFVHy5IeP5a3IIeiICib98saH9sI0j2zlxvid5/eoe+uLnTu0HSsrVEieZA3EokJNPVggWLKloH4Sq/l8deaMTPSUlA9Xlvuvrwoydwpm8dYnRhi5dbuJBjxUPkzhVeE8XwtsHPJhXADzwOTez1RYVi3RywrHHwiNoO/Y8X8ip989Ll1ZjnQpNjYTySvcDpIk3+/xrkPnDEG+5yUXQh74+R5idMXRAoxKqNwWXDls8ZDwrI1vTMaqaN5RrFSBh56PXPN761T5Ii3T3q2r6JM5rWIOJ7/7APtruAlhlMktlwFVthodpgra/qBnlIJVCO+tsYjR62jHYQaqydo4LRwfwc9gLIvC2nEQ0zM3SZ4uERnQgRndC/fowLb/7BFBCh8JKNwPdaZLdbtbV7WgFNn/nZp8SLsaAq6v2TG3W3YPPMsU0OMZ9W4HR87BombgPW6ZnAWFmFzeWV1lAeXopyKedijDTEMWl8WwLrwTD9LvINNo8iDyp6L2ckDXSibfA1n064Y+KopvigxtA78SRxtG9sz2DtTDt6a4QIEaIrS4a/XSBZM+4io1issjML1TUFWXUylr00T6Yj0ifchSdTfGXRNLhl9G0fUcf/Xdf99hi69+VgdOyseVc6I391dIBRb3QVhJOBRe4SGPjxcyXfh9nCgqLKST8ZD4dQgeCvHAPgM3WgMoRxqfyBBmiDu+SWcoxfaynvWuDWvCkhhLwl2bbfr3dSjRGLBmxpsTMXfXg6HgkBwtKZRKXsediVNqjpRA/ryqh3t/Ie9Zbto+RxMnqZeutCptkE+UgKpi58BFg/B2EpsuZ+DN64OPd9qdk1tEQm7/joS3s75bTy5xybXuUyOzGKErRXNzW2ip92z8SKX3seVHushwOE8F7KUUr36e1z3H6it46bSxm0Ue5Qzlxhj1UD9GaZ/Jd32vzWgY2adkTkemnSoWzAw4L7QV+FC6+KoCG+S/cnnh2Lbh1gXiYdPLgmNDuukjGegHDHeJWfSB9pD6faafEXCsTNK6/DE8Zm2O7loWOlSDh00dbASCjfofHG7+mx1AmOSChKYfhWbNuC5xJmtorEMTXcIfHXLDADPE1s9gyvCgS2J8krH6cP0uKZmVkZyZFnRz4SWZLV9zf6Q7ZFeMWWo2LzSlmipTOTVSRVINMkqEkNlalf4XIoRu5xxvGnQrSyq1Le7IpDq2+vagdFiN+jkjkiGUCXTNodQRmTML2F0qj4qh6Uw+JPxw4gmwRAT8aNkokysSzrUAIJCC7syic1CcMB0OeADF/88wkKa0URbbey/R4mU9rP2hiTtJE36i9Rmq5wV7q4SIz5yF+AVeN85RBBd9qFcIYztEExSn7J3lg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(376011)(36860700010)(1800799021)(82310400023); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 12:59:23.0232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 184162ac-68e3-45ab-48ee-08dc91f1f912 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5642 Received-SPF: permerror client-ip=2a01:111:f403:2009::61f; envelope-from=sai.pavan.boddu@amd.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Read boot-mode value as machine property and propagate that to SLCR.BOOT_MODE register. Signed-off-by: Sai Pavan Boddu Acked-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/arm/xilinx_zynq.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fbe..97b6fd8e35d 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "qom/object.h" #include "exec/tswap.h" #include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -90,6 +91,7 @@ struct ZynqMachineState { MachineState parent; Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; }; static void zynq_write_board_setup(ARMCPU *cpu, @@ -176,6 +178,27 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, return unit; } +static void zynq_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m = ZYNQ_MACHINE(obj); + uint8_t mode = 0; + + if (!strncasecmp(str, "qspi", 4)) { + mode = 1; + } else if (!strncasecmp(str, "sd", 2)) { + mode = 5; + } else if (!strncasecmp(str, "nor", 3)) { + mode = 2; + } else if (!strncasecmp(str, "jtag", 4)) { + mode = 0; + } else { + error_setg(errp, "%s boot mode not supported", str); + return; + } + m->boot_mode = mode; +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); @@ -241,6 +264,7 @@ static void zynq_init(MachineState *machine) /* Create slcr, keep a pointer to connect clocks */ slcr = qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); @@ -372,6 +396,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data) NULL }; MachineClass *mc = MACHINE_CLASS(oc); + ObjectProperty *prop; mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init = zynq_init; mc->max_cpus = ZYNQ_MAX_CPUS; @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data) mc->ignore_memory_transaction_failures = true; mc->valid_cpu_types = valid_cpu_types; mc->default_ram_id = "zynq.ext_ram"; + prop = object_class_property_add_str(oc, "boot-mode", NULL, + zynq_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " jtag qspi sd nor"); + object_property_set_default_str(prop, "qspi"); } static const TypeInfo zynq_machine_type = {