Message ID | 20240622120643.3797539-1-peter.maydell@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 6/22/24 05:06, Peter Maydell wrote: > Hi; here's the latest target-arm pullreq; this is pretty much > just various bugfixes. > > -- PMM > > The following changes since commit 02d9c38236cf8c9826e5c5be61780c4444cb4ae0: > > Merge tag 'pull-tcg-20240619' ofhttps://gitlab.com/rth7680/qemu into staging (2024-06-19 14:00:39 -0700) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240622 > > for you to fetch changes up to 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a: > > hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine (2024-06-21 16:24:46 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue > * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing > * hw/intc/arm_gic: Fix deactivation of SPI lines > * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu > * hw/misc: Set valid access size for Exynos4210 RNG > * hw/arm/sbsa-ref: switch to 1GHz timer frequency > * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine > * hw/arm/virt: allow creation of a second NonSecure UART > * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs > * scripts/coverity-scan/COMPONENTS.md: update component regexes > * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions > * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~