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[95.127.46.33]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3674357fd08sm2514150f8f.27.2024.06.27.10.14.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Jun 2024 10:14:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Luc Michel , Francisco Iglesias , qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Vincent Palatin , Sai Pavan Boddu , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [RFC PATCH 19/19] hw/sd/sdcard: Add boot config support Date: Thu, 27 Jun 2024 19:10:59 +0200 Message-ID: <20240627171059.84349-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240627171059.84349-1-philmd@linaro.org> References: <20240627171059.84349-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Joel Stanley Introduced "boot-config" property to set CSD 179, the boot config register. With this correctly set we can use the enable bit to detect if partition support is enabled. Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index bbf054ea1e..b598974bbf 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -129,6 +129,7 @@ struct SDState { uint8_t spec_version; BlockBackend *blk; bool aspeed_emmc_kludge; + uint8_t boot_config; const SDProto *proto; @@ -505,6 +506,8 @@ static void mmc_set_ext_csd(SDState *sd, uint64_t size) sd->ext_csd[159] = 0x00; /* Max enhanced area size */ sd->ext_csd[158] = 0x00; /* ... */ sd->ext_csd[157] = 0xEC; /* ... */ + + sd->ext_csd[EXT_CSD_PART_CONFIG] = sd->boot_config; } static void sd_emmc_set_csd(SDState *sd, uint64_t size) @@ -1004,8 +1007,14 @@ static uint32_t sd_emmc_bootpart_offset(SDState *sd) { unsigned int access = sd->ext_csd[EXT_CSD_PART_CONFIG] & EXT_CSD_PART_CONFIG_ACC_MASK; + unsigned int enable = sd->ext_csd[EXT_CSD_PART_CONFIG] & + EXT_CSD_PART_CONFIG_EN_MASK; unsigned int boot_capacity = sd_boot_capacity_bytes(sd); + if (!enable) { + return 0; + } + switch (access) { case EXT_CSD_PART_CONFIG_ACC_DEFAULT: return boot_capacity * 2; @@ -2808,6 +2817,7 @@ static Property sd_properties[] = { * whether card should be in SSI or MMC/SD mode. It is also up to the * board to ensure that ssi transfers only occur when the chip select * is asserted. */ + DEFINE_PROP_UINT8("boot-config", SDState, boot_config, 0x0), DEFINE_PROP_END_OF_LIST() };