diff mbox series

[v2] target/loongarch: Remove avail_64 in trans_srai_w() and simplify it

Message ID 20240628033357.50027-1-chris.chenfeiyang@gmail.com (mailing list archive)
State New, archived
Headers show
Series [v2] target/loongarch: Remove avail_64 in trans_srai_w() and simplify it | expand

Commit Message

Feiyang Chen June 28, 2024, 3:33 a.m. UTC 
Since srai.w is a valid instruction on la32, remove the avail_64 check
and simplify trans_srai_w().

Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Feiyang Chen <chris.chenfeiyang@gmail.com>
---
 target/loongarch/tcg/insn_trans/trans_shift.c.inc | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

Comments

Feiyang Chen July 10, 2024, 2:43 a.m. UTC | #1 
ping

https://lore.kernel.org/qemu-devel/20240628033357.50027-1-chris.chenfeiyang@gmail.com/

On Fri, Jun 28, 2024 at 1:34 PM Feiyang Chen
<chris.chenfeiyang@gmail.com> wrote:
>
> Since srai.w is a valid instruction on la32, remove the avail_64 check
> and simplify trans_srai_w().
>
> Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only instructions")
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Feiyang Chen <chris.chenfeiyang@gmail.com>
> ---
>  target/loongarch/tcg/insn_trans/trans_shift.c.inc | 15 +++------------
>  1 file changed, 3 insertions(+), 12 deletions(-)
>
> diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> index 2f4bd6ff28..377307785a 100644
> --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> @@ -67,19 +67,9 @@ static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
>      tcg_gen_rotr_tl(dest, src1, t0);
>  }
>
> -static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
> +static void gen_sari_w(TCGv dest, TCGv src1, target_long imm)
>  {
> -    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> -    TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
> -
> -    if (!avail_64(ctx)) {
> -        return false;
> -    }
> -
> -    tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
> -    gen_set_gpr(a->rd, dest, EXT_NONE);
> -
> -    return true;
> +    tcg_gen_sextract_tl(dest, src1, imm, 32 - imm);
>  }
>
>  TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
> @@ -94,6 +84,7 @@ TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
>  TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
>  TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
>  TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
> +TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
>  TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
>  TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
>  TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
> --
> 2.34.1
>
gaosong July 10, 2024, 3:08 a.m. UTC | #2 
在 2024/7/10 上午10:43, Feiyang Chen 写道:
> ping
>
> https://lore.kernel.org/qemu-devel/20240628033357.50027-1-chris.chenfeiyang@gmail.com/
Hi,

I'll be pushing the LoongArch patches this week.

Thanks.
Song Gao
> h
> On Fri, Jun 28, 2024 at 1:34 PM Feiyang Chen
> <chris.chenfeiyang@gmail.com> wrote:
>> Since srai.w is a valid instruction on la32, remove the avail_64 check
>> and simplify trans_srai_w().
>>
>> Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only instructions")
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Feiyang Chen <chris.chenfeiyang@gmail.com>
>> ---
>>   target/loongarch/tcg/insn_trans/trans_shift.c.inc | 15 +++------------
>>   1 file changed, 3 insertions(+), 12 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
>> index 2f4bd6ff28..377307785a 100644
>> --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
>> +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
>> @@ -67,19 +67,9 @@ static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
>>       tcg_gen_rotr_tl(dest, src1, t0);
>>   }
>>
>> -static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
>> +static void gen_sari_w(TCGv dest, TCGv src1, target_long imm)
>>   {
>> -    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
>> -    TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
>> -
>> -    if (!avail_64(ctx)) {
>> -        return false;
>> -    }
>> -
>> -    tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
>> -    gen_set_gpr(a->rd, dest, EXT_NONE);
>> -
>> -    return true;
>> +    tcg_gen_sextract_tl(dest, src1, imm, 32 - imm);
>>   }
>>
>>   TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
>> @@ -94,6 +84,7 @@ TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
>>   TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
>>   TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
>>   TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
>> +TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
>>   TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
>>   TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
>>   TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
>> --
>> 2.34.1
>>
diff mbox series

Patch

diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
index 2f4bd6ff28..377307785a 100644
--- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
@@ -67,19 +67,9 @@  static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
     tcg_gen_rotr_tl(dest, src1, t0);
 }
 
-static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
+static void gen_sari_w(TCGv dest, TCGv src1, target_long imm)
 {
-    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
-    TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
-
-    if (!avail_64(ctx)) {
-        return false;
-    }
-
-    tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
-    gen_set_gpr(a->rd, dest, EXT_NONE);
-
-    return true;
+    tcg_gen_sextract_tl(dest, src1, imm, 32 - imm);
 }
 
 TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
@@ -94,6 +84,7 @@  TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
 TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
 TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
 TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
+TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
 TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
 TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
 TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)