[2/3] target/riscv: zimop instruction encoding and its implementation

Commit Message

Deepak Gupta June 28, 2024, 6:01 p.m. UTC

This patch adds assigned codepoints for decoder for 32bit instructions
and provide implementation for instruction. If extension is present,
then moves 0 to `rd`.

Signed-off-by: Deepak Gupta <[e-mail]>
---
 target/riscv/insn32.decode                 | 15 +++++++
 target/riscv/insn_trans/trans_zimops.c.inc | 50 ++++++++++++++++++++++
 target/riscv/translate.c                   |  3 ++
 3 files changed, 68 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_zimops.c.inc

Patch

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..fca3838a9f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -167,6 +167,21 @@  csrrwi   ............     ..... 101 ..... 1110011 @csr
 csrrsi   ............     ..... 110 ..... 1110011 @csr
 csrrci   ............     ..... 111 ..... 1110011 @csr
 
+# zimops (unpriv integer may be operations) instructions with system opcode
+# zimops_r and zimops_rr are two code points assigned to zimops
+# Any new extension that claims zimops encoding should be placed above mop.r
+# and mop.rr
+
+# mop.r
+{
+  zimops_r   1-00--0 111--     ----- 100 ..... 1110011 %rd
+}
+
+# mop.rr
+{
+  zimops_rr  1-00--1 -----     ----- 100 ..... 1110011 %rd
+}
+
 # *** RV64I Base Instruction Set (in addition to RV32I) ***
 lwu      ............   ..... 110 ..... 0000011 @i
 ld       ............   ..... 011 ..... 0000011 @i
diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
new file mode 100644
index 0000000000..b5ad7bded8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_zimops.c.inc
@@ -0,0 +1,50 @@ 
+/*
+ * RISC-V translation routines for the Control-Flow Integrity Extension
+ *
+ * Copyright (c) 2024 Rivos Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+static bool trans_zimops_r(DisasContext *ctx, arg_zimops_r * a)
+{
+    /* zimops not implemented, raise illegal instruction & return true */
+    if (!ctx->cfg_ptr->ext_zimops) {
+        gen_exception_illegal(ctx);
+        return true;
+    }
+    /*
+     * zimops implemented, simply grab destination and mov zero.
+     * return true
+     */
+    TCGv dest = dest_gpr(ctx, a->rd);
+    dest = tcg_constant_tl(0);
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
+
+static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
+{
+    /* zimops not implemented, raise illegal instruction & return true */
+    if (!ctx->cfg_ptr->ext_zimops) {
+        gen_exception_illegal(ctx);
+        return true;
+    }
+    /*
+     * zimops implemented, simply grab destination and mov zero.
+     * return true
+     */
+    TCGv dest = dest_gpr(ctx, a->rd);
+    dest = tcg_constant_tl(0);
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2c27fd4ce1..b7fd3456c8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1115,6 +1115,9 @@  static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 /* Include decoders for factored-out extensions */
 #include "decode-XVentanaCondOps.c.inc"
 
+/* Include decoder for zimop */
+#include "insn_trans/trans_zimops.c.inc"
+
 /* The specification allows for longer insns, but not supported by qemu. */
 #define MAX_INSN_LEN  4