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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c91d3b9349sm5531698a91.37.2024.06.30.19.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jun 2024 19:51:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH 3/5] target/i386: Rearrange CCOp Date: Sun, 30 Jun 2024 19:51:13 -0700 Message-Id: <20240701025115.1265117-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701025115.1265117-1-richard.henderson@linaro.org> References: <20240701025115.1265117-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Define CC_OP_{FIRST,LAST}_BWLQ. Remove CC_OP_NB. Give the first few enumerators explicit integer constants. Move CC_OP_POPCNT up in the enumeration; remove unused CC_OP_POPCNT*__ placeholders. Align the BWLQ enumerators. This will be used to simplify ((op - CC_OP_*B) & 3). Signed-off-by: Richard Henderson --- target/i386/cpu.h | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 29daf37048..df4272fdae 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1270,14 +1270,27 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, * are only needed for conditional branches. */ typedef enum { - CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ - CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ - CC_OP_ADOX, /* CC_SRC2 = O, CC_SRC = rest. */ - CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ - CC_OP_CLR, /* Z and P set, all other flags clear. */ + CC_OP_DYNAMIC = 0, /* must use dynamic code to get cc_op */ + CC_OP_EFLAGS = 1, /* all cc are explicitly computed, CC_SRC = flags */ + CC_OP_ADCX = 2, /* CC_DST = C, CC_SRC = rest. */ + CC_OP_ADOX = 3, /* CC_SRC2 = O, CC_SRC = rest. */ + CC_OP_ADCOX = 4, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ + CC_OP_CLR = 5, /* Z and P set, all other flags clear. */ - CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ + /* + * Z via CC_DST, all other flags clear. + * Treat CC_OP_POPCNT like the other BWLQ ops in making the low bits + * equal MO_TL; this gives a value of either 6 or 7. + */ +#ifdef TARGET_X86_64 + CC_OP_POPCNT = 7, +#else + CC_OP_POPCNT = 6, +#endif + +#define CC_OP_FIRST_BWLQ CC_OP_POPCNT + + CC_OP_MULB = 8, /* modify all flags, C, O = (CC_SRC != 0) */ CC_OP_MULW, CC_OP_MULL, CC_OP_MULQ, @@ -1332,20 +1345,11 @@ typedef enum { CC_OP_BMILGL, CC_OP_BMILGQ, - /* - * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size) - * is used or implemented, because the translation needs - * to zero-extend CC_DST anyway. - */ - CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear. */ - CC_OP_POPCNTW__, - CC_OP_POPCNTL__, - CC_OP_POPCNTQ__, - CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__, - - CC_OP_NB, +#define CC_OP_LAST_BWLQ CC_OP_BMILGQ } CCOp; -QEMU_BUILD_BUG_ON(CC_OP_NB >= 128); + +/* See X86DecodedInsn.cc_op, using int8_t. */ +QEMU_BUILD_BUG_ON(CC_OP_LAST_BWLQ > INT8_MAX); typedef struct SegmentCache { uint32_t selector;