From patchwork Thu Jul 4 03:16:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E983C2BD09 for ; Thu, 4 Jul 2024 03:02:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPCj1-0004r2-8T; Wed, 03 Jul 2024 23:01:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPCiV-0004LH-2A; Wed, 03 Jul 2024 23:01:05 -0400 Received: from mgamail.intel.com ([198.175.65.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPCiS-0003xS-Jh; Wed, 03 Jul 2024 23:01:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720062061; x=1751598061; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WvA5kdecwjQmICQjAc3CQ0RARFRwW0D39pFCdSGsMJs=; b=AAz7zRtw+PdJRxCmdn6NHnHY3s896NDjK2NbHDSTT+nri//k9S9T5+nj eoDMYtXO2QdJwF6rmwmxZGRMfNRiJp5+mybVFlTV2FoVwQLN4bi8guIK+ cbcJEfLEDChq44Xnki5YmXcy+Vug1eohxFtNFhME32sHyHPKfGqogOaw0 lVUMvQjaJHYXnr2q92eyZ0ZMovk/iKvynYMMSAsz/R0m+6S9Iiwd1yqFY yFW2U+pqkZo/m6nCIeUovpJ+uZGLVjRdIgf9bBpESze1yX174ZjGzzGIR Cj4U8cV3wM48pkndVvBMB2LZdyFtbMIC/mmXqjlcnS2prSfE6YsJO/8KZ g==; X-CSE-ConnectionGUID: H094cRz3QySIafF/6z+GfQ== X-CSE-MsgGUID: cYg9M2oCSSeQYevEgwpyhw== X-IronPort-AV: E=McAfee;i="6700,10204,11122"; a="39838131" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="39838131" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2024 20:00:58 -0700 X-CSE-ConnectionGUID: QYzkN/9dTKaDrPxBswrhTQ== X-CSE-MsgGUID: iWwTKPgkQhy4cReKgVsBCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052354" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:53 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 5/8] i386/cpu: Support thread and module level cache topology Date: Thu, 4 Jul 2024 11:16:00 +0800 Message-Id: <20240704031603.1744546-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allows cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ae3bbf30682..0ddbfa577caf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPO_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPO_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); }