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[7/8] i386/pc: Support cache topology in -machine for PC machine

Message ID 20240704031603.1744546-8-zhao1.liu@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce SMP Cache Topology | expand

Commit Message

Zhao Liu July 4, 2024, 3:16 a.m. UTC 
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since RFC v2:
 * Used cache_supported array.
---
 hw/i386/pc.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 77415064c62e..1614a3b1bf19 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1773,6 +1773,10 @@  static void pc_machine_class_init(ObjectClass *oc, void *data)
     mc->nvdimm_supported = true;
     mc->smp_props.dies_supported = true;
     mc->smp_props.modules_supported = true;
+    mc->smp_props.cache_supported[SMP_CACHE_L1D] = true;
+    mc->smp_props.cache_supported[SMP_CACHE_L1I] = true;
+    mc->smp_props.cache_supported[SMP_CACHE_L2] = true;
+    mc->smp_props.cache_supported[SMP_CACHE_L3] = true;
     mc->default_ram_id = "pc.ram";
     pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;