| Message ID | 20240711-smcntrpmf_v7-v8-3-b7c38ae7b263@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V ISA extension smcntrpmf support | expand |
On Fri, Jul 12, 2024 at 8:33 AM Atish Patra <atishp@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > This adds the properties for ISA extension smcntrpmf. Patches > implementing it will follow. > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4760cb2cc17f..63f553c92b00 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index fb7eebde523b..b1376beb1dab 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -74,6 +74,7 @@ struct RISCVCPUConfig { > bool ext_ztso; > bool ext_smstateen; > bool ext_sstc; > + bool ext_smcntrpmf; > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot; > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4760cb2cc17f..63f553c92b00 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fb7eebde523b..b1376beb1dab 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -74,6 +74,7 @@ struct RISCVCPUConfig { bool ext_ztso; bool ext_smstateen; bool ext_sstc; + bool ext_smcntrpmf; bool ext_svadu; bool ext_svinval; bool ext_svnapot;