| Message ID | 20240711131822.3909903-1-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 7/11/24 06:17, Peter Maydell wrote: > The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf: > > Merge tag 'pull-aspeed-20240709' ofhttps://github.com/legoater/qemu into staging (2024-07-09 07:13:55 -0700) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240711 > > for you to fetch changes up to 7f49089158a4db644fcbadfa90cd3d30a4868735: > > target/arm: Convert PMULL to decodetree (2024-07-11 11:41:34 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Refactor FPCR/FPSR handling in preparation for FEAT_AFP > * More decodetree conversions > * target/arm: Use cpu_env in cpu_untagged_addr > * target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() > * hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() > * hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops > * accel/tcg: MakeTCGCPUOps::cpu_exec_halt mandatory > * STM32L4x5: Handle USART interrupts correctly Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf: Merge tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu into staging (2024-07-09 07:13:55 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240711 for you to fetch changes up to 7f49089158a4db644fcbadfa90cd3d30a4868735: target/arm: Convert PMULL to decodetree (2024-07-11 11:41:34 +0100) ---------------------------------------------------------------- target-arm queue: * Refactor FPCR/FPSR handling in preparation for FEAT_AFP * More decodetree conversions * target/arm: Use cpu_env in cpu_untagged_addr * target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() * hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() * hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops * accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory * STM32L4x5: Handle USART interrupts correctly ---------------------------------------------------------------- Inès Varhol (3): hw/misc: In STM32L4x5 EXTI, consolidate 2 constants hw/misc: In STM32L4x5 EXTI, handle direct interrupts hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI Peter Maydell (12): target/arm: Correct comments about M-profile FPSCR target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr} target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr} target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR target/arm: Implement store_cpu_field_low32() macro target/arm: Store FPSR and FPCR in separate CPU state fields target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically target/arm: Allow FPCR bits that aren't in FPSCR target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory Richard Henderson (7): target/arm: Use cpu_env in cpu_untagged_addr target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree target/arm: Convert PMULL to decodetree Zheyu Ma (2): hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops include/hw/core/tcg-cpu-ops.h | 9 +- include/hw/misc/stm32l4x5_exti.h | 4 +- target/arm/cpu.h | 113 ++-- target/arm/internals.h | 3 + target/arm/tcg/translate-a32.h | 7 + target/arm/tcg/translate.h | 3 +- target/riscv/internals.h | 3 + target/arm/tcg/a64.decode | 77 +++ accel/tcg/cpu-exec.c | 11 +- hw/arm/stm32l4x5_soc.c | 24 +- hw/char/pl011.c | 13 +- hw/misc/bcm2835_thermal.c | 2 + hw/misc/stm32l4x5_exti.c | 13 +- target/alpha/cpu.c | 1 + target/arm/cpu.c | 2 +- target/arm/machine.c | 135 ++++- target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/mve_helper.c | 12 +- target/arm/tcg/translate-a64.c | 1155 ++++++++++++------------------------- target/arm/tcg/translate-m-nocp.c | 22 +- target/arm/tcg/translate-vfp.c | 4 +- target/arm/vfp_helper.c | 187 +++--- target/avr/cpu.c | 1 + target/cris/cpu.c | 2 + target/hppa/cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 2 + target/riscv/cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 39 files changed, 893 insertions(+), 929 deletions(-)