@@ -84,6 +84,13 @@ static int rcount_immhb(DisasContext *s, int x)
return (16 << size) - x;
}
+/* For Advanced SIMD shift by immediate, left shift count. */
+static int lcount_immhb(DisasContext *s, int x)
+{
+ int size = esz_immh(s, x >> 3);
+ return x - (8 << size);
+}
+
/*
* Include the generated decoders.
*/
@@ -6962,6 +6969,8 @@ TRANS(URSHR_v, do_vec_shift_imm, a, gen_gvec_urshr)
TRANS(SRSRA_v, do_vec_shift_imm, a, gen_gvec_srsra)
TRANS(URSRA_v, do_vec_shift_imm, a, gen_gvec_ursra)
TRANS(SRI_v, do_vec_shift_imm, a, gen_gvec_sri)
+TRANS(SHL_v, do_vec_shift_imm, a, tcg_gen_gvec_shli)
+TRANS(SLI_v, do_vec_shift_imm, a, gen_gvec_sli);
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
* Note that it is the caller's responsibility to ensure that the
@@ -10427,33 +10436,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
}
-/* SHL/SLI - Vector shift left */
-static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
- int immh, int immb, int opcode, int rn, int rd)
-{
- int size = 32 - clz32(immh) - 1;
- int immhb = immh << 3 | immb;
- int shift = immhb - (8 << size);
-
- /* Range of size is limited by decode: immh is a non-zero 4 bit field */
- assert(size >= 0 && size <= 3);
-
- if (extract32(immh, 3, 1) && !is_q) {
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (insert) {
- gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size);
- } else {
- gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size);
- }
-}
-
/* USHLL/SHLL - Vector shift left with widening */
static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
int immh, int immb, int opcode, int rn, int rd)
@@ -10566,9 +10548,6 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0x0a: /* SHL / SLI */
- handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
- break;
case 0x10: /* SHRN */
case 0x11: /* RSHRN / SQRSHRUN */
if (is_u) {
@@ -10609,6 +10588,7 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
case 0x04: /* SRSHR / URSHR (rounding) */
case 0x06: /* SRSRA / URSRA (accum + rounding) */
case 0x08: /* SRI */
+ case 0x0a: /* SHL / SLI */
unallocated_encoding(s);
return;
}
@@ -1191,9 +1191,12 @@ FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
%abcdefgh 16:3 5:5
%esz_immh 19:4 !function=esz_immh
%rcount_immhb 16:7 !function=rcount_immhb
+%lcount_immhb 16:7 !function=lcount_immhb
@qrshifti . q:1 .. ..... .... ... ..... . rn:5 rd:5 \
&qrri_e esz=%esz_immh imm=%rcount_immhb
+@qlshifti . q:1 .. ..... .... ... ..... . rn:5 rd:5 \
+ &qrri_e esz=%esz_immh imm=%lcount_immhb
FMOVI_v_h 0 q:1 00 1111 00000 ... 1111 11 ..... rd:5 %abcdefgh
@@ -1212,5 +1215,8 @@ FMOVI_v_h 0 q:1 00 1111 00000 ... 1111 11 ..... rd:5 %abcdefgh
SRSRA_v 0.00 11110 .... ... 00110 1 ..... ..... @qrshifti
URSRA_v 0.10 11110 .... ... 00110 1 ..... ..... @qrshifti
SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @qrshifti
+
+ SHL_v 0.00 11110 .... ... 01010 1 ..... ..... @qlshifti
+ SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @qlshifti
]
}
This includes SHL and SLI. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 40 +++++++++------------------------- target/arm/tcg/a64.decode | 6 +++++ 2 files changed, 16 insertions(+), 30 deletions(-)