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[92.88.170.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a6efc5sm60849745e9.21.2024.07.19.11.12.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jul 2024 11:12:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Mark Cave-Ayland , Tong Ho , Manos Pitsidianakis , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v5 14/16] hw/char/pl011: Consider TX FIFO overrun error Date: Fri, 19 Jul 2024 20:10:39 +0200 Message-ID: <20240719181041.49545-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240719181041.49545-1-philmd@linaro.org> References: <20240719181041.49545-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When transmission is disabled, characters are still queued to the FIFO which eventually overruns. Report that error condition in the status register. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/pl011.c | 17 +++++++++++++++++ hw/char/trace-events | 1 + 2 files changed, 18 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 6394d6eb36..b8cde03f98 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -61,6 +61,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) /* Data Register, UARTDR */ #define DR_BE (1 << 10) +/* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ +#define RSR_OE (1 << 3) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -232,6 +235,13 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque) int bytes_consumed; uint8_t data; + if (!(s->cr & CR_UARTEN)) { + qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled UART\n"); + } + if (!(s->cr & CR_TXE)) { + qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX UART\n"); + } + data = fifo8_pop(&s->xmit_fifo); bytes_consumed = 1; @@ -257,6 +267,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data) qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX UART\n"); } + if (fifo8_is_full(&s->xmit_fifo)) { + /* The FIFO is already full. Content remains valid. */ + trace_pl011_fifo_tx_overrun(); + s->rsr |= RSR_OE; + return; + } + trace_pl011_fifo_tx_put(data); pl011_loopback_tx(s, data); fifo8_push(&s->xmit_fifo, data); diff --git a/hw/char/trace-events b/hw/char/trace-events index 30d06a2383..4a9c0bd271 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -62,6 +62,7 @@ pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]" pl011_fifo_tx_xmit(int count) "TX FIFO pop %d chars" +pl011_fifo_tx_overrun(void) "TX FIFO overrun" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" # cmsdk-apb-uart.c