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[92.88.170.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d6929976sm33385325e9.29.2024.07.19.11.12.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jul 2024 11:12:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Mark Cave-Ayland , Tong Ho , Manos Pitsidianakis , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Mikko Rapeli Subject: [RFC PATCH v5 16/16] hw/char/pl011: Implement TX FIFO Date: Fri, 19 Jul 2024 20:10:41 +0200 Message-ID: <20240719181041.49545-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240719181041.49545-1-philmd@linaro.org> References: <20240719181041.49545-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If the UART back-end chardev doesn't drain data as fast as stdout does or blocks, buffer in the TX FIFO to try again later. This avoids having the IO-thread busy waiting on chardev back-ends, reported recently when testing the Trusted Reference Stack and using the socket backend. Implement registering a front-end 'watch' callback on back-end events, so we can resume transmitting when the back-end is writable again, not blocking the main loop. Similarly to the RX FIFO path, FIFO level selection is not implemented (interrupt is triggered when a single byte is available in the FIFO). Reported-by: Mikko Rapeli Suggested-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- RFC: Something is still broken, some characters are emitted async... --- hw/char/pl011.c | 60 ++++++++++++++++++++++++++++++++++++-------- hw/char/trace-events | 1 + 2 files changed, 51 insertions(+), 10 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index cfa3fd3da4..9f72b6a765 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -240,7 +240,9 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque) { PL011State *s = opaque; int bytes_consumed; - uint8_t data; + const uint8_t *buf; + uint32_t buflen; + uint32_t count; if (!(s->cr & CR_UARTEN)) { qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled UART\n"); @@ -249,25 +251,40 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque) qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX UART\n"); } + count = fifo8_num_used(&s->xmit_fifo); + if (count < 1) { + /* FIFO empty */ + return G_SOURCE_REMOVE; + } + if (!qemu_chr_fe_backend_connected(&s->chr)) { /* Instant drain the fifo when there's no back-end. */ pl011_drain_tx(s); return G_SOURCE_REMOVE; } - data = fifo8_pop(&s->xmit_fifo); - bytes_consumed = 1; + buf = fifo8_peek_buf(&s->xmit_fifo, count, &buflen); - /* - * XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks - */ - qemu_chr_fe_write_all(&s->chr, &data, bytes_consumed); + /* Transmit as much data as we can. */ + bytes_consumed = qemu_chr_fe_write(&s->chr, buf, buflen); trace_pl011_fifo_tx_xmit(bytes_consumed); + if (bytes_consumed < 0) { + /* Error in back-end: drain the fifo. */ + pl011_drain_tx(s); + return G_SOURCE_REMOVE; + } + + /* Pop the data we could transmit. */ + fifo8_pop_buf(&s->xmit_fifo, bytes_consumed, NULL); s->int_level |= INT_TX; pl011_update(s); + if (!fifo8_is_empty(&s->xmit_fifo)) { + /* Reschedule another transmission if we couldn't transmit all. */ + return G_SOURCE_CONTINUE; + } + return G_SOURCE_REMOVE; } @@ -290,6 +307,10 @@ static void pl011_write_txdata(PL011State *s, uint8_t data) trace_pl011_fifo_tx_put(data); pl011_loopback_tx(s, data); fifo8_push(&s->xmit_fifo, data); + if (fifo8_is_full(&s->xmit_fifo)) { + s->flags |= PL011_FLAG_TXFF; + } + pl011_xmit(NULL, G_IO_OUT, s); } @@ -488,10 +509,24 @@ static void pl011_write(void *opaque, hwaddr offset, pl011_trace_baudrate_change(s); break; case 11: /* UARTLCR_H */ - /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & LCR_FEN) { - pl011_reset_rx_fifo(s); + bool fifo_enabled = value & LCR_FEN; + + trace_pl011_fifo_enable(fifo_enabled); + if (fifo_enabled) { + /* Transmit and receive FIFO buffers are enabled (FIFO mode). */ + fifo8_change_capacity(&s->xmit_fifo, PL011_FIFO_DEPTH); + } else { + /* + * FIFOs are disabled (character mode) that is, the FIFOs + * become 1-byte-deep holding registers. + */ + pl011_drain_tx(s); + fifo8_change_capacity(&s->xmit_fifo, 1); + } + /* Reset the FIFO state on FIFO enable or disable */ pl011_reset_tx_fifo(s); + pl011_reset_rx_fifo(s); } if ((s->lcr ^ value) & LCR_BRK) { int break_enable = value & LCR_BRK; @@ -636,6 +671,11 @@ static int pl011_post_load(void *opaque, int version_id) s->read_pos = 0; } + if (!fifo8_is_empty(&s->xmit_fifo)) { + /* Reschedule another transmission */ + qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, pl011_xmit, s); + } + s->ibrd &= IBRD_MASK; s->fbrd &= FBRD_MASK; diff --git a/hw/char/trace-events b/hw/char/trace-events index bf586ba664..2405819812 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -58,6 +58,7 @@ pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x valu pl011_read_fifo(int read_count) "FIFO read, read_count now %d" pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" +pl011_fifo_enable(bool enable) "enable:%u" pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"