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[92.88.170.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-368787cedabsm2217831f8f.84.2024.07.19.11.11.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jul 2024 11:11:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Mark Cave-Ayland , Tong Ho , Manos Pitsidianakis , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson Subject: [PATCH v5 07/16] hw/char/pl011: Extract pl011_read_rxdata() from pl011_read() Date: Fri, 19 Jul 2024 20:10:32 +0200 Message-ID: <20240719181041.49545-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240719181041.49545-1-philmd@linaro.org> References: <20240719181041.49545-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org To keep MemoryRegionOps read/write handlers with similar logic, factor pl011_read_txdata() out of pl011_read(), similar to what the previous commit did to pl011_write(). No functional change intended. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/char/pl011.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c2ee9b0321..5e44837206 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -233,31 +233,38 @@ static void pl011_write_txdata(PL011State *s, uint8_t data) pl011_update(s); } +static uint32_t pl011_read_rxdata(PL011State *s) +{ + uint32_t c; + + s->flags &= ~PL011_FLAG_RXFF; + c = s->read_fifo[s->read_pos]; + if (s->read_count > 0) { + s->read_count--; + s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); + } + if (s->read_count == 0) { + s->flags |= PL011_FLAG_RXFE; + } + if (s->read_count == s->read_trigger - 1) { + s->int_level &= ~ INT_RX; + } + trace_pl011_read_fifo(s->read_count); + s->rsr = c >> 8; + pl011_update(s); + qemu_chr_fe_accept_input(&s->chr); + return c; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { PL011State *s = (PL011State *)opaque; - uint32_t c; uint64_t r; switch (offset >> 2) { case 0: /* UARTDR */ - s->flags &= ~PL011_FLAG_RXFF; - c = s->read_fifo[s->read_pos]; - if (s->read_count > 0) { - s->read_count--; - s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); - } - if (s->read_count == 0) { - s->flags |= PL011_FLAG_RXFE; - } - if (s->read_count == s->read_trigger - 1) - s->int_level &= ~ INT_RX; - trace_pl011_read_fifo(s->read_count); - s->rsr = c >> 8; - pl011_update(s); - qemu_chr_fe_accept_input(&s->chr); - r = c; + r = pl011_read_rxdata(s); break; case 1: /* UARTRSR */ r = s->rsr;