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([10.4.50.11]) by sgspiesaa002.seagate.com with ESMTP; 22 Jul 2024 13:17:37 -0700 From: Alejandro Zeise To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, alejandro.zeise@seagate.com, clg@kaod.org, peter.maydell@linaro.org, berrange@redhat.com Subject: [PATCH 2/2] hw/misc/aspeed_hace: Fix SG Accumulative hashing Date: Mon, 22 Jul 2024 20:15:24 +0000 Message-Id: <20240722201524.822730-3-alejandro.zeise@seagate.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240722201524.822730-1-alejandro.zeise@seagate.com> References: <20240722201524.822730-1-alejandro.zeise@seagate.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000C:EE_|MW4PR20MB5227:EE_ X-MS-Office365-Filtering-Correlation-Id: 87f2f9e3-3a37-4b47-5fc8-08dcaa8b58d8 STX-Hosted-IronPort-Oubound: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: OFmt4TmYpBQMWOyxbBdKG18s/wdrtI1zijHtb0uEJJA3ubtP/+GuqjdYHEFXzQX5wknWJZibmjau8OG/z7KFH5UENlikO1QM7P4ZOom8UpGzYvFGA0LmEUkg7AYVXAhmM7AXZnZHjOenv/BYUqTBAiAztYFV+36+ZiSs2MJlcRNIb56Da6OWEo9JvwQWCIuPHDxR4ummTbloND5AkwJdQhGm/OLAuYaEAfAjxWN06BAOIeZNQ64eWtvK6OBAY8DhPH3mzuUiPtFMUZ1e/ljBV5gddSeyoRXEOoTfBwGUtJUsXX84F6j9k+74d8tOF6Q2KC2vz5RhInTgGzPIjZ16uFdU2dO2PvcCj5AmwOXIdj/g0ZMkOq07j8lhehnX+KDt9DpvQNyehyupaylsL5wfZ4DhE2tTQhIBlQcrisyfY7wAy6GYlgGBA0mQHhBsOd5C7GkDLp3gaxCGu5m03ve/t/UwP7R8RG9DA0rMKwfcIN96yxLr7X2jlkTP/PrLoYQ9s98V+NJD6mqSDp+7/LocVOpRWDnCu48VDE1Bx05vMik+kVb9CMgCRy8jiv+cIXqATv2P5/v6RNNm4b+9nnvV8D5hffQGhYAeeBkM6TVVgz5SrMm1Z8j2k2lddrMpyA0RUIicZ0+MNRULN5lv/nBiAX1bW3v7XqqQBgnu3vVzc3Xtc69vieHyjv6O4VAI6vEvEUaLgurU5QgnK4b5yFjh6T4K70fIWRkrrT+ILvS8Z+fZfRrvhdRxvwyFX/TltNp7hti9CfvAmymwlomO6Vdfg2KYnOMWb3dnzt9aQXMinxq4bFWG5ZjKf01AzPajDR0QFZ85NmoBwy3SuZ7FV4xLcDFEnfk/Pgh2lcHIGmqOn+FWGcaakXX3otzPk05zry6Xaz1ETTXdaOorlzhoxVcP/hnjsqnaf2CY2eHLRknBMCVo/fEvPVrdiIexwJ8a9K6wXVm+G11yp4ZA9avqPc7TR/ntme7Lq6VyWKY2XHDVNhZ7tQur0Sdx9xV+43aBWIuo09+nANxuUuDEjQFrN4TdtlZkFnkej5BLpjLG6D22niM6lstzDeQC9Pa0v/BcBQl+kM9SvpdnHw/KvdgjPjz63VIiZyTfTDT3i038y/S7OSYEW9JZ3is/nXRNhsmmG3XG8tR7zOvr5tkWrhB9CHPdPGWvqFnxDSuMMjI2FhU/FF9EADzyIJRFh946+xRo1c6+qkz968bgC6fI32v1AMIKqKeYejkyzeu+/DLomgxfH+1Qy+iYY/F5RzItnB4PzZJvPV5349mJdLB3G4piQeKK8l8uB7l1Bv/io8PhT49bM14jKXK0K3comivolcFiBCQFX75VzPQtqyt5ZgCb5TeGSvHoaLrY8jDrb2mrSt41STkX4LRbD2bBH2/D4PM4qOZ2 X-Forefront-Antispam-Report: CIP:192.55.16.50; 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Ip=[192.55.16.50]; Helo=[sgspzesaa001.seagate.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR20MB5227 Received-SPF: pass client-ip=216.71.153.94; envelope-from=alejandro.zeise@seagate.com; helo=esa.hc4959-67.iphmx.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.133, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 22 Jul 2024 17:21:20 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash could be computed once the final chunk was received. However, the cache was a shallow copy, so once the guest overwrote the memory provided to HACE the final hash would not be correct. Possibly related to: https://gitlab.com/qemu-project/qemu/-/issues/1121 Buglink: https://github.com/openbmc/qemu/issues/36 Signed-off-by: Alejandro Zeise --- hw/misc/aspeed_hace.c | 91 ++++++++++++++++++----------------- include/hw/misc/aspeed_hace.h | 4 ++ 2 files changed, 51 insertions(+), 44 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index c06c04ddc6..8306d8986a 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -1,6 +1,7 @@ /* * ASPEED Hash and Crypto Engine * + * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates * Copyright (C) 2021 IBM Corp. * * Joel Stanley @@ -151,47 +152,15 @@ static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id, return iov_count; } -/** - * Generate iov for accumulative mode. - * - * @param s aspeed hace state object - * @param iov iov of the current request - * @param id index of the current iov - * @param req_len length of the current request - * - * @return count of iov - */ -static int gen_acc_mode_iov(AspeedHACEState *s, struct iovec *iov, int id, - hwaddr *req_len) -{ - uint32_t pad_offset; - uint32_t total_msg_len; - s->total_req_len += *req_len; - - if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { - if (s->iov_count) { - return reconstruct_iov(s, iov, id, &pad_offset); - } - - *req_len -= s->total_req_len - total_msg_len; - s->total_req_len = 0; - iov[id].iov_len = *req_len; - } else { - s->iov_cache[s->iov_count].iov_base = iov->iov_base; - s->iov_cache[s->iov_count].iov_len = *req_len; - ++s->iov_count; - } - - return id + 1; -} - static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { struct iovec iov[ASPEED_HACE_MAX_SG]; + uint32_t total_msg_len; + uint32_t pad_offset; g_autofree uint8_t *digest_buf = NULL; size_t digest_len = 0; - int niov = 0; + bool sg_acc_mode_final_request = false; int i; void *haddr; @@ -226,8 +195,15 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, } iov[i].iov_base = haddr; if (acc_mode) { - niov = gen_acc_mode_iov(s, iov, i, &plen); - + s->total_req_len += plen; + + if (has_padding(s, &iov[i], plen, &total_msg_len, &pad_offset)) { + /* Padding being present indicates the final request */ + sg_acc_mode_final_request = true; + iov[i].iov_len = pad_offset; + } else { + iov[i].iov_len = plen; + } } else { iov[i].iov_len = plen; } @@ -252,20 +228,42 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, * required to check whether cache is empty. If no, we should * combine cached iov and the current iov. */ - uint32_t total_msg_len; - uint32_t pad_offset; s->total_req_len += len; if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) { - niov = reconstruct_iov(s, iov, 0, &pad_offset); + i = reconstruct_iov(s, iov, 0, &pad_offset); } } } - if (niov) { - i = niov; - } + if (acc_mode) { + if (s->qcrypto_hash_context == NULL && + qcrypto_hash_accumulate_new_ctx(algo, &s->qcrypto_hash_context, NULL)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto failed to create hash context\n", + __func__); + return; + } + + if (qcrypto_hash_accumulate_bytesv(algo, + s->qcrypto_hash_context, iov, i, + &digest_buf, + &digest_len, NULL) < 0) { + + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } - if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) < 0) { + if (sg_acc_mode_final_request) { + if (qcrypto_hash_accumulate_free_ctx(s->qcrypto_hash_context, NULL) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: qcrypto failed to free context\n", __func__); + } + + s->qcrypto_hash_context = NULL; + s->iov_count = 0; + s->total_req_len = 0; + } + } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) < 0) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); return; } @@ -397,6 +395,11 @@ static void aspeed_hace_reset(DeviceState *dev) { struct AspeedHACEState *s = ASPEED_HACE(dev); + if (s->qcrypto_hash_context != NULL) { + qcrypto_hash_accumulate_free_ctx(s->qcrypto_hash_context, NULL); + s->qcrypto_hash_context = NULL; + } + memset(s->regs, 0, sizeof(s->regs)); s->iov_count = 0; s->total_req_len = 0; diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index ecb1b67de8..b3c2eb17b7 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -1,6 +1,7 @@ /* * ASPEED Hash and Crypto Engine * + * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates * Copyright (C) 2021 IBM Corp. * * SPDX-License-Identifier: GPL-2.0-or-later @@ -10,6 +11,7 @@ #define ASPEED_HACE_H #include "hw/sysbus.h" +#include "crypto/hash.h" #define TYPE_ASPEED_HACE "aspeed.hace" #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" @@ -35,6 +37,8 @@ struct AspeedHACEState { MemoryRegion *dram_mr; AddressSpace dram_as; + + qcrypto_hash_accumulate_ctx_t *qcrypto_hash_context; };