From patchwork Thu Jul 25 23:45:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 13742219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C1C3C3DA49 for ; Thu, 25 Jul 2024 23:47:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sX8AV-0000Ot-0s; Thu, 25 Jul 2024 19:46:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sX8AK-0008Ba-Rj for qemu-devel@nongnu.org; Thu, 25 Jul 2024 19:46:32 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sX8AI-0005JW-Am for qemu-devel@nongnu.org; Thu, 25 Jul 2024 19:46:32 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-70d333d57cdso351582b3a.3 for ; Thu, 25 Jul 2024 16:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721951189; x=1722555989; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7bXtglqSyDHmhS5ymxp0JdF77BUhuOGby1CsDo/HdPw=; b=ZIodFY7P//V0NkiByheexHRgEHWnZ3aI7h/LgznjjGoUJbMl9p7ecT9JP/7w61eih7 ImLS+bTAYZ9Gdc/S92fiqmFk28+xbAasZxd+/IxoCVDAoSda3ghC/w25RVc0oKOJKYAZ Q61CLOVVNVvrmGiLkUeHSIcFp5yPhAqrq3/aGslGEaEE7HePqVS55kAy7hLdJ5db6Wca rKN9Itu3dSPY0pS+IBDPnsbscw2t6n9xZUP5jshQpeINrAVorekqxLpiQQ7RhUQfTkjH zEAwPwD3NzupOrBUn5x4eiGA4IPc95Fd43WKqopYT5SIDqhX4zeg58wNjBxkaIDuk2XQ MSgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721951189; x=1722555989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7bXtglqSyDHmhS5ymxp0JdF77BUhuOGby1CsDo/HdPw=; b=eA/619w4iOjpTtyhhA4tyqEP+KUzRdCvXNeta9ybpDcQ847taw7SQ0E5s4Zv8RGSth LUqd63BUaw4R0bYMG5o6WaIZEVd7qw32qxDwdqY6B0658HxC6eVwKX5zFLAL/Zb1Dych 3z3w07rWiGQo6c8o7U9SRiOYHMW037++cGQ89qt6oyHDeLGtO9iciNhURpVlS1e5KAuQ aINVLUYMGhIsS4jtx7tZIS71N6cKDY2Kqs/HNPoHuRMkt2KmXFGtUboaIT7uk4MjjvxT TJ3KCY2j350dXD87ZQ2JL4ornpKirmHH+B6vDYy+lnVEBKEA/w3+5tebdK0NslXzQhOk Fe7Q== X-Forwarded-Encrypted: i=1; AJvYcCVYu7gbIQQAeLjyN7djjdpXtObMzYqViCJPn6fSW2gKf3Zh2TBQV37mBegqpxyn10HckJM/wWHabiRasfzKwzhLaLIQbwo= X-Gm-Message-State: AOJu0YwS0flcGum3IZruEa0hsCA9g8c7jVR9zVfc0vZpVIVrvAbenJaz FgTL5+Ow1zfYtSu9BBRJm+zJ2jcKafX95FHUgEIl5D+QGd2Z/zje/zVDXcnkDCk= X-Google-Smtp-Source: AGHT+IH79Iancu76ub8oB4UGBzx/GrcnI0TlRmEG7QLhNoNsEo92RT8t+YbwYSi3/bGkdSZQNbSrDw== X-Received: by 2002:a05:6a00:2d8c:b0:70e:8070:f9d0 with SMTP id d2e1a72fcca58-70eae8d5c8amr4597113b3a.9.1721951188849; Thu, 25 Jul 2024 16:46:28 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70ead8128d0sm1647565b3a.118.2024.07.25.16.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jul 2024 16:46:28 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, jim.shu@sifive.com, andy.chiu@sifive.com, jesse.huang@sifive.com, kito.cheng@sifive.com Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta Subject: [PATCH 04/24] target/riscv: additional code information for sw check Date: Thu, 25 Jul 2024 16:45:53 -0700 Message-ID: <20240725234614.3850142-5-debug@rivosinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240725234614.3850142-1-debug@rivosinc.com> References: <20240725234614.3850142-1-debug@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=debug@rivosinc.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Signed-off-by: Deepak Gupta --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 ++ target/riscv/csr.c | 1 + 3 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c7841fc08..12334f9540 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,6 +224,8 @@ struct CPUArchState { /* elp state for zicfilp extension */ cfi_elp elp; + /* sw check code for sw check exception */ + target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; bool ufcfien; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fb4b6066d3..41bc73ad60 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1762,6 +1762,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) cs->watchpoint_hit = NULL; } break; + case RISCV_EXCP_SW_CHECK: + tval = env->sw_check_code; default: break; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5771a14848..a5a969a377 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1179,6 +1179,7 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_SW_CHECK)) | \ (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \