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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70ead6e1a4bsm2002128b3a.5.2024.07.25.22.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jul 2024 22:59:50 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Jason Wang , qemu-arm@nongnu.org (open list:Xilinx Zynq), Jim Shu Subject: [PATCH 4/4] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX Date: Fri, 26 Jul 2024 13:59:33 +0800 Message-Id: <20240726055933.817-5-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726055933.817-1-jim.shu@sifive.com> References: <20240726055933.817-1-jim.shu@sifive.com> Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=jim.shu@sifive.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When AXI ethernet RX is disabled, it shouldn't send packets to AXI DMA, which may let AXI DMA to send RX full IRQs. It is aligned with real AXI DMA/ethernet IP behavior in the FPGA. Also, now ethernet RX blocks the RX packets when it is disabled. It should send and clear the remaining RX packets when enabling it. Signed-off-by: Jim Shu --- hw/net/xilinx_axienet.c | 71 ++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 05d41bd548..8428f10946 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -530,6 +530,40 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) return r; } +static void axienet_eth_rx_notify(void *opaque) +{ + XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); + + /* If RX is disabled, don't trigger DMA to update RX desc and send IRQ */ + if (!axienet_rx_enabled(s)) { + return; + } + + while (s->rxappsize && stream_can_push(s->tx_control_dev, + axienet_eth_rx_notify, s)) { + size_t ret = stream_push(s->tx_control_dev, + (void *)s->rxapp + CONTROL_PAYLOAD_SIZE + - s->rxappsize, s->rxappsize, true); + s->rxappsize -= ret; + } + + while (s->rxsize && stream_can_push(s->tx_data_dev, + axienet_eth_rx_notify, s)) { + size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, + s->rxsize, true); + s->rxsize -= ret; + s->rxpos += ret; + if (!s->rxsize) { + s->regs[R_IS] |= IS_RX_COMPLETE; + if (s->need_flush) { + s->need_flush = false; + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + } + } + enet_update_irq(s); +} + static void enet_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -546,6 +580,14 @@ static void enet_write(void *opaque, hwaddr addr, } else { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } + + /* + * When RX is enabled, check if any remaining data in rxmem + * and send them. + */ + if ((addr & 1) && s->rcw[addr & 1] & RCW1_RX) { + axienet_eth_rx_notify(s); + } break; case R_TC: @@ -666,35 +708,6 @@ static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) return match; } -static void axienet_eth_rx_notify(void *opaque) -{ - XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); - - while (s->rxappsize && stream_can_push(s->tx_control_dev, - axienet_eth_rx_notify, s)) { - size_t ret = stream_push(s->tx_control_dev, - (void *)s->rxapp + CONTROL_PAYLOAD_SIZE - - s->rxappsize, s->rxappsize, true); - s->rxappsize -= ret; - } - - while (s->rxsize && stream_can_push(s->tx_data_dev, - axienet_eth_rx_notify, s)) { - size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, - s->rxsize, true); - s->rxsize -= ret; - s->rxpos += ret; - if (!s->rxsize) { - s->regs[R_IS] |= IS_RX_COMPLETE; - if (s->need_flush) { - s->need_flush = false; - qemu_flush_queued_packets(qemu_get_queue(s->nic)); - } - } - } - enet_update_irq(s); -} - static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { XilinxAXIEnet *s = qemu_get_nic_opaque(nc);