From patchwork Mon Jul 29 17:53:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 13745544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BCBEC3DA61 for ; Mon, 29 Jul 2024 17:54:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sYUYz-0004JY-MO; Mon, 29 Jul 2024 13:53:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sYUYy-0004Fp-Gu for qemu-devel@nongnu.org; Mon, 29 Jul 2024 13:53:36 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sYUYv-0000G5-R8 for qemu-devel@nongnu.org; Mon, 29 Jul 2024 13:53:36 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-70d333d5890so3420016b3a.0 for ; Mon, 29 Jul 2024 10:53:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1722275612; x=1722880412; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xTvsa+ViAqHINj5oJb/iz6qO9j2BBr+FG4wAjwt7ac=; b=zGySS8ddTlZ3FcloOHLtgwzyfqhZ2fK7iXmPQjhiaM6yFWtqIH/9ETzy1nR950G1OI lUCwJSg9PVgsXjGb07MUtSKm5qRnEPg5dw5Z0xxF74DyK+gLAO+0B5z5ufDQKBBN2hQT e6cnvSft1GQnnrv0FwMQBwvTPzQdfGWkrd2va1CV0kojzI57p4aTBxwE4onWkYsbSvkP Bf2T6upWwFD0h/9Y3JD0nxolpAt5zko+exjmGsxTxrmIay39DZEzrmuwPB3TbsI3lCJW ytBvZ5v1wR9GOLVRo/o3dbPCttM/5j8FdeWe8dX7OAWUdYrfOasnKHFnq8VPkELfblIi tfBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722275612; x=1722880412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xTvsa+ViAqHINj5oJb/iz6qO9j2BBr+FG4wAjwt7ac=; b=dx5ITHHz3OKfVlUe8na8RJYx1s4dfjXAU81jLMvCxus/uPzjE+UPG8EcNpz9o9+FVD /aHFC+3Ai678j3qyhpYLVr05EljhEjAuphSNORCmkwrfbFVn+JAgh/iMk0eceEr1hg6Z fHP8S1YX6UnbbdmakQ1N8h7j6LlwDKbdpMtmyuQHoKXSAoe16Qp6W7qjOkU5InfjVt7W sm5J71izB8+e2XLcx3Ba1oCbGH7F9pXEXp86tcGYKjiI+g6pOmdrAjWO19n3XaJMXx2e D2No5kbskPTJ69mKvDIq3doAbjhFt9R/NVu8eT9Wh9qagUScJBmDsI+jgZ0Zyios7wog x6Ag== X-Forwarded-Encrypted: i=1; AJvYcCWjSkNd1OhbZymp+NOtKwzKQVR772Zp3im8JgX8qxL5WnJJ2vUIxeP6YGt+o7JThFTXXG2L/4AyApdgzsONaqlctvnIzig= X-Gm-Message-State: AOJu0Yzu0ZKYeQMAO07FRixVY8kDrodvbsQk4HVFemZbOlsvDnWoq7Zn 9W0Bru6cpSgR3c27/3ywpn8ZM+dRYBPXoc16CXtmp4tdyOOfVv1XjolqLgqsbCo= X-Google-Smtp-Source: AGHT+IHlxDv7T7dlyFBO0GeoP4OnZ+IMFt+Tx1Grgpd8Tusa/3dtoC6YxWv/NGU93esvXdaH3HoCfg== X-Received: by 2002:a05:6a21:32a1:b0:1c2:94d5:2ee8 with SMTP id adf61e73a8af0-1c4a129e6femr11577316637.17.1722275612212; Mon, 29 Jul 2024 10:53:32 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f7c71b15sm6303141a12.18.2024.07.29.10.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 10:53:31 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, jim.shu@sifive.com, andy.chiu@sifive.com, jesse.huang@sifive.com, kito.cheng@sifive.com Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta Subject: [PATCH v2 01/24] target/riscv: Add zicfilp extension Date: Mon, 29 Jul 2024 10:53:03 -0700 Message-ID: <20240729175327.73705-2-debug@rivosinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240729175327.73705-1-debug@rivosinc.com> References: <20240729175327.73705-1-debug@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=debug@rivosinc.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33ef4eb795..5dfb3f39ab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -106,6 +106,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), @@ -1472,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), + MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 120905a254..88d5defbb5 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -67,6 +67,7 @@ struct RISCVCPUConfig { bool ext_zicbom; bool ext_zicbop; bool ext_zicboz; + bool ext_zicfilp; bool ext_zicond; bool ext_zihintntl; bool ext_zihintpause; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b8814ab753..ed19586c9d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -623,6 +623,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->pmu_avail_ctrs = 0; } + if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { + error_setg(errp, "zicfilp extension requires zicsr extension"); + return; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need.