| Message ID | 20240802072417.659-4-zhiwei_liu@linux.alibaba.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Remove redundant insn length check for zama16b | expand |
On 8/2/24 17:24, LIU Zhiwei wrote: > According to the risc-v specification: > "FLD and FSD are only guaranteed to execute atomically if the effective > address is naturally aligned and XLEN≥64." > > We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does > not violate the rules. But it will hide some problems. So relax it to > MO_ATOM_NONE. > > Signed-off-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com> > --- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Fri, Aug 2, 2024 at 5:27 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote: > > According to the risc-v specification: > "FLD and FSD are only guaranteed to execute atomically if the effective > address is naturally aligned and XLEN≥64." > > We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does > not violate the rules. But it will hide some problems. So relax it to > MO_ATOM_NONE. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc > index 49682292b8..8a46124f98 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -48,11 +48,17 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) > REQUIRE_EXT(ctx, RVD); > > /* > - * Zama16b applies to loads and stores of no more than MXLEN bits defined > - * in the F, D, and Q extensions. > + * FLD and FSD are only guaranteed to execute atomically if the effective > + * address is naturally aligned and XLEN≥64. Also, zama16b applies to > + * loads and stores of no more than MXLEN bits defined in the F, D, and > + * Q extensions. > */ > - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { > + if (get_xl_max(ctx) == MXL_RV32) { > + memop |= MO_ATOM_NONE; > + } else if (ctx->cfg_ptr->ext_zama16b) { > memop |= MO_ATOM_WITHIN16; > + } else { > + memop |= MO_ATOM_IFALIGN; > } > > decode_save_opc(ctx); > @@ -71,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > > - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { > + if (get_xl_max(ctx) == MXL_RV32) { > + memop |= MO_ATOM_NONE; > + } else if (ctx->cfg_ptr->ext_zama16b) { > memop |= MO_ATOM_WITHIN16; > + } else { > + memop |= MO_ATOM_IFALIGN; > } > > decode_save_opc(ctx); > -- > 2.25.1 > >
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 49682292b8..8a46124f98 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -48,11 +48,17 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_EXT(ctx, RVD); /* - * Zama16b applies to loads and stores of no more than MXLEN bits defined - * in the F, D, and Q extensions. + * FLD and FSD are only guaranteed to execute atomically if the effective + * address is naturally aligned and XLEN≥64. Also, zama16b applies to + * loads and stores of no more than MXLEN bits defined in the F, D, and + * Q extensions. */ - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) == MXL_RV32) { + memop |= MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ATOM_IFALIGN; } decode_save_opc(ctx); @@ -71,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) == MXL_RV32) { + memop |= MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ATOM_IFALIGN; } decode_save_opc(ctx);
According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> --- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)