| Message ID | 20240802083423.142365-14-itachis@FreeBSD.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | bsd-user: Comprehensive RISCV support | expand |
On 8/2/24 18:34, Ajeet Singh wrote: > From: Warner Losh<imp@bsdimp.com> > > Added a generic definition for RISC-V64 target-specific details. > Implemented the 'regpairs_aligned' function,which returns 'false' > to indicate that register pairs are not aligned in the RISC-V64 ABI. > > Signed-off-by: Warner Losh<imp@bsdimp.com> > Signed-off-by: Ajeet Singh<itachis@FreeBSD.org> > --- > bsd-user/riscv/target.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 bsd-user/riscv/target.h Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h new file mode 100644 index 0000000000..036ddd185e --- /dev/null +++ b/bsd-user/riscv/target.h @@ -0,0 +1,20 @@ +/* + * Riscv64 general target stuff that's common to all aarch details + * + * Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_H +#define TARGET_H + +/* + * riscv64 ABI does not 'lump' the registers for 64-bit args. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return false; +} + +#endif /* TARGET_H */